Patents by Inventor Yasushi Haga
Yasushi Haga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080061380Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.Type: ApplicationFiled: October 31, 2007Publication date: March 13, 2008Applicant: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20080064169Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.Type: ApplicationFiled: October 31, 2007Publication date: March 13, 2008Applicant: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Patent number: 6916714Abstract: A procedure of manufacturing a semiconductor device according to the present invention first creates a gate electrode on a center portion of a gate oxide film formed on a substrate, forms a silicon oxide film over the whole surface of the substrate including the gate electrode, and etches the whole face of the silicon oxide film, so as to form a side wall of the silicon oxide film on a side face of the gate electrode. The procedure then implants an impurity ion according to a channel of a target MOS transistor, so as to specify a drain area and a source area. In the process of specifying the drain area and the source area, a resist is formed in advance on at least a peripheral portion of the gate oxide film in a high-breakdown-voltage MOS transistor, so as to prevent implantation of the impurity ion in an under-layer region below the peripheral portion of the gate oxide film.Type: GrantFiled: August 2, 2002Date of Patent: July 12, 2005Assignee: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20040256677Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistors' characteristics. At first, an insulating film is formed. The insulating film protions above the drain and source formation regions fo rhte high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.Type: ApplicationFiled: July 16, 2004Publication date: December 23, 2004Applicant: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20040238858Abstract: [Problem]To reduce a leakage current by suppressing the generation of a junction leakage.Type: ApplicationFiled: March 11, 2004Publication date: December 2, 2004Inventors: Yasushi Haga, Muneyoshi Hama
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Patent number: 6780701Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistor's characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.Type: GrantFiled: October 11, 2002Date of Patent: August 24, 2004Assignee: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Patent number: 6720222Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 for defining side walls is subsequently formed on the whole surface of the substrate 100 in a greater thickness of approximately 2000 angstrom than a standard thickness. Over-etching of the sixth oxide film 119 defines side walls 119SW. Non-required portions of the oxide film 112 are then etched off with a resist R15A. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15A is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region.Type: GrantFiled: October 17, 2002Date of Patent: April 13, 2004Assignee: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Patent number: 6638804Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 to define a side wall is subsequently formed on the whole surface of the substrate 100, and a resist R17 is formed over the whole high-breakdown-voltage transistor area HV. Over-etching of the low-breakdown-voltage transistor area LV is carried out to make the surface of the substrate 100 exposed and to define the side wall only in the low-breakdown-voltage transistor area LV. The oxide film 119 is made to remain in the high-breakdown-voltage transistor area HV. Non-required portions of the oxide films 119 and 112 are then etched off with a resist R15B.Type: GrantFiled: October 17, 2002Date of Patent: October 28, 2003Assignee: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20030082866Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 for defining side walls is subsequently formed on the whole surface of the substrate 100 in a greater thickness of approximately 2000 angstrom than a standard thickness. Over-etching of the sixth oxide film 119 defines side walls 119SW. Non-required portions of the oxide film 112 are then etched off with a resist R15A. This causes a drain-source forming region, which is expected to form a drain area and a source area, to be open in an element forming region in a high-breakdown-voltage nMOS area HVn. The resist R15A is not removed but is used continuously, and an n-type impurity ion is implanted into the open drain-source forming region.Type: ApplicationFiled: October 17, 2002Publication date: May 1, 2003Applicant: SEIKO EPSON CORPORATIONInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20030080354Abstract: The present invention provides a technique for efficiently forming a high-breakdown voltage transistor and a low-breakdown voltage transistor on the same substrate while reducing the deterioration of each transistor's characteristics. At first, an insulating film is formed. The insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor are thicker than those for the low-breakdown voltage transistor. Next, gates are formed on the insulating film. Then sidewalls are formed on the sides of the low-breakdown voltage transistor gate, and apertures are made in the insulating film portions above the drain and source formation regions for each transistor. When apertures are made in the relatively thick insulating film portions above the drain and source formation regions for the high-breakdown voltage transistor, etching is performed not to narrow widths of the sidewalls formed on the sides of the gate for the low-breakdown voltage transistor.Type: ApplicationFiled: October 11, 2002Publication date: May 1, 2003Applicant: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20030077865Abstract: Among first and second oxide films 110 and 112 formed on a substrate 100, the oxide film in a low-breakdown-voltage transistor area LV is all etched off, while the whole surface of the oxide film in a high-breakdown-voltage transistor area HV is left intact. A sixth oxide film 119 to define a side wall is subsequently formed on the whole surface of the substrate 100, and a resist R17 is formed over the whole high-breakdown-voltage transistor area HV. Over-etching of the low-breakdown-voltage transistor area LV is carried out to make the surface of the substrate 100 exposed and to define the side wall only in the low-breakdown-voltage transistor area LV. The oxide film 119 is made to remain in the high-breakdown-voltage transistor area HV. Non-required portions of the oxide films 119 and 112 are then etched off with a resist R15B.Type: ApplicationFiled: October 17, 2002Publication date: April 24, 2003Applicant: Seiko Epson CorporationInventors: Atsushi Kanda, Yasushi Haga
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Publication number: 20030034531Abstract: A procedure of manufacturing a semiconductor device according to the present invention first creates a gate electrode on a center portion of a gate oxide film formed on a substrate, forms a silicon oxide film over the whole surface of the substrate including the gate electrode, and etches the whole face of the silicon oxide film, so as to form a side wall of the silicon oxide film on a side face of the gate electrode. The procedure then implants an impurity ion according to a channel of a target MOS transistor, so as to specify a drain area and a source area. In the process of specifying the drain area and the source area, a resist is formed in advance on at least a peripheral portion of the gate oxide film in a high-breakdown-voltage MOS transistor, so as to prevent implantation of the impurity ion in an under-layer region below the peripheral portion of the gate oxide film.Type: ApplicationFiled: August 2, 2002Publication date: February 20, 2003Applicant: SEIKO EPSON CORPORATIONInventors: Atsushi Kanda, Yasushi Haga