Patents by Inventor Yasushi Hashizume

Yasushi Hashizume has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7497541
    Abstract: An apparatus discharges a discharge liquid in the form of droplets from apertures by mechanically deforming piezoelectric elements by a normal drive signal. The droplets are discharged from the apertures by a cooling drive signal, which is different from the normal drive signal.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: March 3, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Hidenori Usuda, Yasushi Hashizume, Yasuhiro Hiraide
  • Patent number: 7362194
    Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: April 22, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
  • Publication number: 20070146089
    Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.
    Type: Application
    Filed: February 20, 2007
    Publication date: June 28, 2007
    Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
  • Patent number: 7202754
    Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: April 10, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
  • Patent number: 7064411
    Abstract: A spiral inductor in which, where a spiral interconnect and an underpass interconnect intersect with each other, at least one layer of an electrically conductive film that forms the spiral interconnect is the underpass interconnect. The spiral interconnect has a smaller number of electrically conductive layers in the intersecting portion and has a wider interconnect width than the spiral interconnect in a non-intersecting portion.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: June 20, 2006
    Assignee: Mitsubishi Denki kabushiki Kaisha
    Inventors: Yasushi Hashizume, Kazuyasu Nishikawa
  • Publication number: 20060071732
    Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitive element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.
    Type: Application
    Filed: November 17, 2005
    Publication date: April 6, 2006
    Applicant: RENESAS TECHNOLOGY CORPORATION
    Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
  • Publication number: 20050247999
    Abstract: A semiconductor device includes: an inductor (1) provided with a conductor interconnection formed spirally on a semiconductor substrate (10); and a shield (6a) that is provided with a continuous conductor interconnection provided along the outer periphery of the spiral pattern of the inductor (1) while opening a portion of the conductor interconnection, and that is electrically connected to ground potential.
    Type: Application
    Filed: May 29, 2003
    Publication date: November 10, 2005
    Inventors: Kazuyasu Nishikawa, Yasushi Hashizume
  • Publication number: 20050073025
    Abstract: A spiral inductor in which, where a spiral interconnect and an underpass interconnect intersect with each other, at least one layer of an electrically conductive film that forms the spiral interconnect is the underpass interconnect. The spiral interconnect has a smaller number of electrically conductive layers in the intersecting portion and has a wider interconnect width than the spiral interconnect a non-intersecting portion.
    Type: Application
    Filed: February 4, 2003
    Publication date: April 7, 2005
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasushi Hashizume, Kazuyasu Nishikawa
  • Publication number: 20040183606
    Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.
    Type: Application
    Filed: August 21, 2003
    Publication date: September 23, 2004
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
  • Publication number: 20040135831
    Abstract: An apparatus discharges a discharge liquid in the form of droplets from apertures by mechanically deforming piezoelectric elements by a normal drive signal. The droplets are discharged from the apertures by a cooling drive signal, which is different from the normal drive signal.
    Type: Application
    Filed: October 30, 2003
    Publication date: July 15, 2004
    Inventors: Hidenori Usuda, Yasushi Hashizume, Yasuhiro Hiraide
  • Patent number: 6495928
    Abstract: A transfer mark structure for a multi-layer interconnecting process for avoiding the influence of dishing when a groove pattern for multi-layer interconnection is formed, and for improving the accuracy and stability of reading the transfer mark used for transfer in the following step so as to align with a location of transfer in the preceding step, and a method for producing such a transfer mark for the multi-layer interconnecting process. The underlying layer 102 immediately under the transfer mark 22 for photoengraving formed in the step of connecting between interconnecting layers 16 has a groove-like pattern.
    Type: Grant
    Filed: December 21, 1999
    Date of Patent: December 17, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasushi Hashizume, Takahisa Eimori
  • Patent number: 5604145
    Abstract: Transfer gate transistors are formed on a main surface of a semiconductor substrate. The transfer gate transistors have impurity regions for serving as source/drain regions. A first interlayer insulating film having a substantially flat upper surface is formed to cover the transfer gate transistors. The first interlayer insulating film is provided with contact holes reaching the impurity regions. Plugs are formed in the contact holes. Capacitors are only formed on the flat upper surface of the first interlayer insulating film. Lower electrodes of the capacitors and the plugs are electrically connected with each other through barrier layers. Thus, it is possible to improve capacitances of capacitors in a DRAM.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: February 18, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasushi Hashizume, Hiroki Shinkawata
  • Patent number: 5436477
    Abstract: Transfer gate transistors are formed on a main surface of a semiconductor substrate. The transfer gate transistors have impurity regions for serving as source/drain regions. A first interlayer insulating film having a substantially flat upper surface is formed to cover the transfer gate transistors. The first interlayer insulating film is provided with contact holes reaching the impurity regions. Plugs are formed in the contact holes. Capacitors are only formed on the flat upper surface of the first interlayer insulating film. Lower electrodes of the capacitors and the plugs are electrically connected with each other through barrier layers. Thus, it is possible to improve capacitances of capacitors in a DRAM.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: July 25, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasushi Hashizume, Hiroki Shinkawata
  • Patent number: 5245158
    Abstract: A semiconductor device manufacturing apparatus has a heat retaining tube which can be freely placed in and pulled out of a processing chamber of the apparatus. When located within the processing chamber, the heat retaining tube surrounds a boat with the semiconductor wafers mounted thereon. After the thermal processing of the semiconductor wafers has been completed, the heat retaining tube and the semiconductor wafers are pulled out of the processing chamber together. In this way, the difference in the temperature of the center and periphery of the semiconductor wafer is decreased, and semiconductor devices, which have excellent performance and which are free from crystalline defects or dislocation, can thus be manufactured.
    Type: Grant
    Filed: September 30, 1991
    Date of Patent: September 14, 1993
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasushi Hashizume, Mitsuhiro Tomikawa