Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: A terminating resistance element of an LSI chip has an N? type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N? type impurity diffusion region, and a pair of electrodes formed at respective ends at the surface of the N+ type impurity diffusion layer. The N? type impurity diffusion region has an impurity concentration lower than the impurity concentration of the N+ type impurity diffusion layer. Therefore, the capacitance of the PN junction becomes smaller as compared to the conventional case where the N type impurity diffusion layer is provided directly at the surface of a P type semiconductor substrate. Therefore, reflection and attenuation of an input signal are suppressed.

Abstract: A terminating resistance element of an LSI chip has an N? type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N? type impurity diffusion region, and a pair of electrodes formed at respective ends at the surface of the N+ type impurity diffusion layer. The N? type impurity diffusion region has an impurity concentration lower than the impurity concentration of the N+ type impurity diffusion layer. Therefore, the capacitance of the PN junction becomes smaller as compared to the conventional case where the N type impurity diffusion layer is provided directly at the surface of a P type semiconductor substrate. Therefore, reflection and attenuation of an input signal are suppressed.

Abstract: PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: A bias voltage generating circuit and a differential amplifier which can ensure a constant current through a constant current circuit in a differential amplifier circuit even in case that a common mode voltage of the reference voltage signal to the differential amplifier circuit changes are attained. A constant current is generated employing a current source (Isw) and a current mirror circuit composed of a transistor (M1 and M2). The constant current is supplied to a source of a transistor (M3). A drain and a gate of a transistor (M4) are connected with a drain of the transistor (M3). A reference voltage signal (Vref) to a differential amplifier circuit is inputted to a gate of the transistor (M3), and a drain potential of the transistor (M4) is made to function as a bias voltage (biasn) to a constant current circuit in the differential amplifier circuit.

Abstract: A bias voltage generating circuit and a differential amplifier which can ensure a constant current through a constant current circuit in a differential amplifier circuit even in case that a common mode voltage of the reference voltage signal to the differential amplifier circuit changes are attained. A constant current is generated employing a current source (Isw) and a current mirror circuit composed of a transistor (M1 and M2). The constant current is supplied to a source of a transistor (M3). A drain and a gate of a transistor (M4) are connected with a drain of the transistor (M3). A reference voltage signal (Vref) to a differential amplifier circuit is inputted to a gate of the transistor (M3), and a drain potential of the transistor (M4) is made to function as a bias voltage (biasn) to a constant current circuit in the differential amplifier circuit.

Abstract: A terminating resistance element of an LSI chip has an N? type impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an N+ type impurity diffusion layer formed at the surface of the N? type impurity diffusion region, and a pair of electrodes formed at respective ends at the surface of the N+ type impurity diffusion layer. The N? type impurity diffusion region has an impurity concentration lower than the impurity concentration of the N+ type impurity diffusion layer. Therefore, the capacitance of the PN junction becomes smaller as compared to the conventional case where the N type impurity diffusion layer is provided directly at the surface of a P type semiconductor substrate. Therefore, reflection and attenuation of an input signal are suppressed.

Abstract: A disc rotor used in a disc brake which generates a vibration having a large component in the axial direction of the disc rotor when a brake pad is pressed against the disc rotor. The disc rotor has a hat portion to be fixed to an axle hub of a vehicle. A sliding portion, which is pressed by a brake pad so as to generate a brake force, is connected to the hat portion via a connecting portion. A plurality of ribs are provided to increase a rigidity of the connecting portion. A low-rigidity portion having a rigidity less than the sliding portion and the connecting portion may be provided between the sliding portion and the connecting portion.

Abstract: It is an object to enlarge the logical amplitude of an output signal of a flip-flop circuit with a suppressed, low power-supply voltage to reduce the possibility of occurrence of malfunction. A signal outputted from a differential amplification portion is converted in an internal level converting circuit and fed back to bases of transistors of a slave latch. With input signals having a high level at 0.5 V, the internal level converting circuit performs conversion to provide output signals having a high level at 0.25 V to prevent a current flowing between a collector and a base of the transistors.

Abstract: A level conversion circuit as a semiconductor integrated circuit has a first load resistance (R1), a second load resistance (R2), a first NMOS transistor (MN3) and a second NMOS transistor (MN4) connected to them (R1 and R2) in parallel, respectively, that are driven directly by positive CMOS level signals, a first bipolar transistor (Q1), and a second bipolar transistor (Q2). Both emitters of the first and second bipolar transistors (Q1 and Q2) are connected commonly, and a voltage potential that is lower than a voltage potential of a collector of the first bipolar transistor (Q1) by a predetermined voltage potential is supplied into a base of the second bipolar transistor (Q2).

Abstract: The power consumption of a flip-flop circuit is reduced and an output magnitude is increased to prevent a malfunction from occurring often. In order to reduce the power consumption, an emitter-coupled logic with series gating is used for the master latch of the flip-flop circuit. A series gating is not used but an ECL having transistors connected in parallel is used for the gates of a slave latch so as to increase the output magnitude.

Abstract: In an ECL circuit, when a potential of an input signal A changes from "L" to "H", an output signal D correspondingly changes from "H" to "L", and, at this time, an output sent from a switching stage circuit is supplied to a gate of a PMOS transistor via a control capacitor. Thereby, a base current of a pull-down transistor flows, and change of a potential of an output terminal node is promoted. An NMOS transistor receiving the potential of the output terminal node is arranged between a node and a VEE supply terminal. Therefore, when the potential changes, the current flowing through a transistor decreases, and the base current of the pull-down transistor further increases, so that the change of the output signal D is further promoted.

Abstract: A clamping circuit (Q.sub.3) provides the second potential (V.sub.EE) with a clamp voltage which remains a constant value even if the second potential (V.sub.EE) varies, to obtain a clamp potential (V.sub.c). A little variation of the clamp voltage due to the variation of the second potential (V.sub.EE) is transferred to a current generating circuit (Q.sub.4) and then a feedback current (I.sub.3) is applied to a feedback circuit (Q.sub.2) in response to the variation of the clamp voltage. Since an output potential (V.sub.O) outputted from an output circuit (Q.sub.1) varies in response to the variation of the second potential (V.sub.EE), an output voltage which is a potential difference between the output potential (V.sub.O) and the second potential (V.sub.EE) remains at a constant value.

Abstract: There is disclosed a signal processing device which includes a pre-processing circuit (31) for performing a serial-to-parallel conversion on an intermediate signal (M.sub.2) at a PECL level, the serial-to-parallel conversion at the PECL level being permitted to deal with a high frequency, and a level converter circuit (12) for performing a conversion from the ECL to PECL levels both having the same logic level width, which conversion consumes less power than a conversion between the ECL and CMOS levels having different logic level widths. The level conversion of a parallel signal requires less power consumed than a level conversion of a serial signal. The signal processing device further includes a level converter circuit (13) for performing a conversion into the CMOS level after obtaining an intermediate signal (M.sub.3) which is a parallel signal. An intermediate signal (M.sub.4) is at the CMOS level and has a low frequency.