Patents by Inventor Yasushi Higuchi

Yasushi Higuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12289917
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, a depth d (?m) of the part embedded in the n?-type semiconductor layer satisfying d?1.4; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: April 29, 2025
    Assignee: FLOSFIA INC.
    Inventors: Mitsuru Okigawa, Fujio Okui, Yasushi Higuchi, Koji Amazutsumi, Hidetaka Shibata, Yuji Kato, Atsushi Terai
  • Patent number: 12284822
    Abstract: There is provided a semiconductor device comprising at least, a crystalline oxide semiconductor layer which has a band gap of 4.5 eV or more; and a field-effect mobility of 10 cm2/V·s or higher.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 22, 2025
    Assignee: FLOSFIA INC.
    Inventors: Masahiro Sugimoto, Yasushi Higuchi
  • Patent number: 12159940
    Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: December 3, 2024
    Assignee: FLOSFIA INC.
    Inventors: Mitsuru Okigawa, Yasushi Higuchi, Yusuke Matsubara, Osamu Imafuji, Takashi Shinohe
  • Publication number: 20240363695
    Abstract: Provided is a semiconductor device including at least: an n type oxide semiconductor layer; a first p type oxide semiconductor layer that forms a main junction with the n type oxide semiconductor layer, and a hole supply layer, wherein the hole supply layer includes a second p type oxide semiconductor layer that is different from the first p type oxide semiconductor layer.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Takashi SHINOHE, Mitsuru OKIGAWA, Koji AMAZUTSUMI, Yasushi HIGUCHI, Tokiyoshi MATSUDA
  • Patent number: 12107137
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 ?m from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: October 1, 2024
    Assignee: FLOSFIA INC.
    Inventors: Mitsuru Okigawa, Fujio Okui, Yasushi Higuchi, Koji Amazutsumi, Hidetaka Shibata, Yuji Kato, Atsushi Terai
  • Publication number: 20240055510
    Abstract: Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer, a drift layer, and a source region; a gate electrode arranged over the channel layer across a gate insulating film; a current blocking region arranged between the channel layer and the drift layer; and a source electrode provided on the source region. The current blocking region is composed of a high-resistance layer. The source electrode forms a contact with the current blocking region.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 15, 2024
    Inventors: Masahiro SUGIMOTO, Shinpei MATSUDA, Yasushi HIGUCHI, Kazuyoshi NORIMATSU
  • Publication number: 20240055471
    Abstract: Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer and a drift layer; and a gate electrode arranged over the channel layer across a gate insulating film, and has a current blocking layer between the channel layer and the drift layer. The semiconductor device is characterized in that the drift layer contains a first crystalline oxide as a major component, the current blocking layer contains a second crystalline oxide as a major component, and the first crystalline oxide and the second crystalline oxide have different compositions.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 15, 2024
    Inventors: Masahiro SUGIMOTO, Shinpei MATSUDA, Yasushi HIGUCHI, Kazuyoshi NORIMATSU
  • Publication number: 20230335581
    Abstract: Provided a semiconductor device having a structure to suppress hole injections into the gate insulator. A semiconductor device including a gate insulating film, a hole blocking layer placed in contact with the gate insulating film, and an oxide semiconductor layer placed in contact with the hole blocking layer, wherein the hole blocking layer is located between the gate insulating film and the oxide semiconductor layer.
    Type: Application
    Filed: June 9, 2023
    Publication date: October 19, 2023
    Inventors: Yasushi HIGUCHI, Takashi SHINOHE
  • Publication number: 20230290832
    Abstract: Provided is a semiconductor device, including: a gate electrode having at least a part buried in a semiconductor layer; a deep p layer having at least a part buried in the semiconductor layer to a same depth as a buried lower end portion of the gate electrode or a position deeper than the buried lower end portion; and a channel layer, wherein: the deep p layer is formed by a crystalline oxide semiconductor; and a carrier concentration of the deep p layer is higher than a carrier concentration of the channel layer.
    Type: Application
    Filed: April 11, 2023
    Publication date: September 14, 2023
    Inventors: Yasushi HIGUCHI, Masahiro SUGIMOTO, Takashi SHINOHE, Isao TAKAHASHI, Hideo MATSUKI, Fusao HIROSE
  • Publication number: 20230253462
    Abstract: Provided is a crystalline oxide film including: a plane tilted from a c-plane as a principal plane; gallium; and a metal in Group 9 of the periodic table, the metal in Group 9 of the periodic table among all metallic elements in the film having an atomic ratio of equal to or less than 23%.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 10, 2023
    Inventors: Takashi SHINOHE, Hiroyuki ANDO, Yasushi HIGUCHI, Shinpei MATSUDA, Kazuya TANIGUCHI, Hiroki WATANABE, Hideo MATSUKI
  • Publication number: 20230123210
    Abstract: Provided is a semiconductor device including: a semiconductor layer; a non-conductive layer that is in contact with at least a part of a side surface of the semiconductor layer directly or via another layer; and a Schottky electrode that is disposed on the semiconductor layer and the non-conductive layer, an end portion of the Schottky electrode being located above the non-conductive layer.
    Type: Application
    Filed: December 5, 2022
    Publication date: April 20, 2023
    Inventors: Takayoshi OSHIMA, Yasushi HIGUCHI
  • Publication number: 20220393037
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, a depth d (?m) of the part embedded in the n?-type semiconductor layer satisfying d?1.4; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 8, 2022
    Inventors: Mitsuru OKIGAWA, Fujio OKUI, Yasushi HIGUCHI, Koji AMAZUTSUMI, Hidetaka SHIBATA, Yuji KATO, Atsushi TERAI
  • Publication number: 20220393015
    Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 ?m from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.
    Type: Application
    Filed: June 7, 2022
    Publication date: December 8, 2022
    Inventors: Mitsuru OKIGAWA, Fujio OKUI, Yasushi HIGUCHI, Koji AMAZUTSUMI, Hidetaka SHIBATA, Yuji KATO, Atsushi TERAI
  • Publication number: 20220293740
    Abstract: Provided is a semiconductor device comprising at least, a high-resistance oxide film, which is placed in a direction in which a current flows, the high-resistance oxide film having a resistance of 1.0×106 ?·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; and a high-resistance oxide film, which is placed between the source electrode and the drain electrode and has a resistance of 1.0×106 ?·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; a high-resistance oxide film; and a substrate with the high-resistance oxide film being placed between the source electrode or/and the drain electrode and the substrate and having a resistance of 1.0×106 ?·cm or higher.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 15, 2022
    Inventors: Masahiro SUGIMOTO, Yasushi HIGUCHI
  • Publication number: 20220285543
    Abstract: There is provided a semiconductor device comprising at least, a crystalline oxide semiconductor layer which has a band gap of 4.5 eV or more; and a field-effect mobility of 10 cm2V·s or higher.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Masahiro SUGIMOTO, Yasushi HIGUCHI
  • Publication number: 20220285557
    Abstract: A semiconductor device including at least a crystalline oxide semiconductor layer, which has a band gap of 3 eV or more and a field-effect mobility of 30 cm2/V·s or higher.
    Type: Application
    Filed: May 27, 2022
    Publication date: September 8, 2022
    Inventors: Masahiro SUGIMOTO, Yasushi HIGUCHI
  • Publication number: 20220246733
    Abstract: An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer, a dielectric film provided on the semiconductor layer and having an opening and provided over a distance of at least 0.25 ?m from the opening, and an electrode layer provided over a part or all of the dielectric film from the inside of the opening, wherein the dielectric film has a thickness of less than 50 nm from the opening to a distance of 0.25 ?m, and has relative permittivity of 5 or less.
    Type: Application
    Filed: May 22, 2020
    Publication date: August 4, 2022
    Inventors: Mitsuru OKIGAWA, Yasushi HIGUCHI, Yusuke MATSUBARA
  • Publication number: 20220158000
    Abstract: Provided is a semiconductor device in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented, the semiconductor device that is particularly useful for power devices. A semiconductor device including at least: a semiconductor layer; a Schottky electrode; and an insulator layer provided between a part of the semiconductor layer and the Schottky electrode, wherein the semiconductor layer contains a crystalline oxide semiconductor, and wherein the insulator layer has a taper angle of 10° or less.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 19, 2022
    Inventors: Mitsuru OKIGAWA, Yasushi HIGUCHI, Yusuke MATSUBARA, Osamu IMAFUJI, Takashi SHINOHE
  • Publication number: 20220140145
    Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Mitsuru OKIGAWA, Yasushi HIGUCHI, Yusuke MATSUBARA, Osamu IMAFUJI, Takashi SHINOHE
  • Patent number: 10714606
    Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: July 14, 2020
    Assignee: DENSO CORPORATION
    Inventors: Youngshin Eum, Kazuhiro Oyama, Yasushi Higuchi, Yoshinori Tsuchiya, Shinichi Hoshi