Abstract: Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer and a drift layer; and a gate electrode arranged over the channel layer across a gate insulating film, and has a current blocking layer between the channel layer and the drift layer. The semiconductor device is characterized in that the drift layer contains a first crystalline oxide as a major component, the current blocking layer contains a second crystalline oxide as a major component, and the first crystalline oxide and the second crystalline oxide have different compositions.

Abstract: Provided a semiconductor device includes at least: a crystalline oxide semiconductor layer including a channel layer, a drift layer, and a source region; a gate electrode arranged over the channel layer across a gate insulating film; a current blocking region arranged between the channel layer and the drift layer; and a source electrode provided on the source region. The current blocking region is composed of a high-resistance layer. The source electrode forms a contact with the current blocking region.

Abstract: Provided a semiconductor device having a structure to suppress hole injections into the gate insulator. A semiconductor device including a gate insulating film, a hole blocking layer placed in contact with the gate insulating film, and an oxide semiconductor layer placed in contact with the hole blocking layer, wherein the hole blocking layer is located between the gate insulating film and the oxide semiconductor layer.

Abstract: Provided is a semiconductor device, including: a gate electrode having at least a part buried in a semiconductor layer; a deep p layer having at least a part buried in the semiconductor layer to a same depth as a buried lower end portion of the gate electrode or a position deeper than the buried lower end portion; and a channel layer, wherein: the deep p layer is formed by a crystalline oxide semiconductor; and a carrier concentration of the deep p layer is higher than a carrier concentration of the channel layer.

Abstract: Provided is a crystalline oxide film including: a plane tilted from a c-plane as a principal plane; gallium; and a metal in Group 9 of the periodic table, the metal in Group 9 of the periodic table among all metallic elements in the film having an atomic ratio of equal to or less than 23%.

Abstract: Provided is a semiconductor device including: a semiconductor layer; a non-conductive layer that is in contact with at least a part of a side surface of the semiconductor layer directly or via another layer; and a Schottky electrode that is disposed on the semiconductor layer and the non-conductive layer, an end portion of the Schottky electrode being located above the non-conductive layer.

Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, the high-resistance layer having a bottom surface located at a distance of less than 1.5 ?m from an upper surface of the n+-type semiconductor layer; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.

Abstract: Provided is a semiconductor device in which a leakage current is reduced, the semiconductor device which is particularly useful for power devices. A semiconductor device including at least: an n+-type semiconductor layer, which contains a crystalline oxide semiconductor as a major component; an n?-type semiconductor layer that is placed on the n+-type semiconductor layer, the n?-type semiconductor layer containing a crystalline oxide semiconductor as a major component; a high-resistance layer with at least a part thereof being embedded in the n?-type semiconductor layer, a depth d (?m) of the part embedded in the n?-type semiconductor layer satisfying d?1.4; and a Schottky electrode that forms a Schottky junction with the n?-type semiconductor layer, the Schottky electrode having an edge located on the high-resistance layer.

Abstract: Provided is a semiconductor device comprising at least, a high-resistance oxide film, which is placed in a direction in which a current flows, the high-resistance oxide film having a resistance of 1.0×106 ?·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; and a high-resistance oxide film, which is placed between the source electrode and the drain electrode and has a resistance of 1.0×106 ?·cm or higher. A semiconductor device comprising at least, a gate electrode; a source electrode; a drain electrode; a high-resistance oxide film; and a substrate with the high-resistance oxide film being placed between the source electrode or/and the drain electrode and the substrate and having a resistance of 1.0×106 ?·cm or higher.

Abstract: There is provided a semiconductor device comprising at least, a crystalline oxide semiconductor layer which has a band gap of 4.5 eV or more; and a field-effect mobility of 10 cm2V·s or higher.

Abstract: A semiconductor device including at least a crystalline oxide semiconductor layer, which has a band gap of 3 eV or more and a field-effect mobility of 30 cm2/V·s or higher.

Abstract: An object of the disclosure is to provide a semiconductor device with low-loss and suppressed leakage current, which is particularly useful for power devices. A semiconductor device including a semiconductor layer, a dielectric film provided on the semiconductor layer and having an opening and provided over a distance of at least 0.25 ?m from the opening, and an electrode layer provided over a part or all of the dielectric film from the inside of the opening, wherein the dielectric film has a thickness of less than 50 nm from the opening to a distance of 0.25 ?m, and has relative permittivity of 5 or less.

Abstract: Provided is a semiconductor device in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented, the semiconductor device that is particularly useful for power devices. A semiconductor device including at least: a semiconductor layer; a Schottky electrode; and an insulator layer provided between a part of the semiconductor layer and the Schottky electrode, wherein the semiconductor layer contains a crystalline oxide semiconductor, and wherein the insulator layer has a taper angle of 10° or less.

Abstract: Provided are a multilayer structure in which crystal defects due to stress concentration in a semiconductor layer caused by an insulator film are prevented and a semiconductor device using the multilayer structure, the multilayer structure and the semiconductor device that are particularly useful for power devices. A multilayer structure in which an insulator film is arranged on a part of a semiconductor film, wherein the semiconductor film has a corundum structure and contains a crystalline oxide semiconductor containing one or two or more metals selected from groups 9 and 13 of the periodic table, and wherein the insulator film has a taper angle of 20° or less.

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.

Abstract: A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.

Abstract: A semiconductor device includes a conductive substrate, a channel forming layer, a first electrode, and a second electrode. The channel forming layer is located above the conductive substrate and includes at least one hetero-junction structure. The hetero-junction structure includes a first GaN-type semiconductor layer providing a drift region and a second GaN-type semiconductor layer having a bandgap energy greater than the first GaN-type semiconductor layer. A total fixed charge quantity of charges in the first GaN-type layer and the second GaN-type layer is from 0.5×1013 to 1.5×1013 cm?2. The charges in the first GaN-type layer and the second GaN-type layer include charges generated by the polarization in the first GaN-type layer. Accordingly, the semiconductor device capable of improving a break-down voltage and decreasing an on-resistance is obtained.

Abstract: In a semiconductor device, an AlGaN layer includes a first AlGaN layer and a second AlGaN layer. The second AlGaN layer is positioned between a gate structure portion and a drain electrode and is divided into multiple parts in an arrangement direction in which the gate structure portion and the drain electrode are arranged. A second Al mixed crystal ratio of the second AlGaN layer is less than a first Al mixed crystal ratio of the first AlGaN layer. Accordingly, the semiconductor device is a normally-off-type device and is capable of restricting a decrease of a breakdown voltage and an increase of an on-resistance.

Abstract: A nitride semiconductor device includes a horizontal switching device that includes a substrate, a channel forming layer, a source region, a drain region and a gate region. The source region and the drain region are arranged apart from each other in one direction along a plane of the substrate. The gate region is formed of a p-type semiconductor layer and is arranged between the source region and the drain region. The gate region is divided into multiple parts in a perpendicular direction along the plane of the substrate, the perpendicular direction being perpendicular to an arrangement direction in which the source region and the drain region are arranged. Accordingly, on-resistance is decreased while securing high breakdown voltage.