Patents by Inventor Yasushi Igarashi

Yasushi Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8188555
    Abstract: A capacitive sensor includes a semiconductor substrate, a fixed electrode serving as a first electrode formed on a surface of or in the semiconductor substrate, a structure formed on the semiconductor substrate to have a vibratable second electrode that is formed to be spaced from and opposed to the semiconductor substrate and from the fixed electrode serving as the first electrode, a sealing member serving as a first sealing member formed on the semiconductor substrate to be spaced from the structure, to cover the structure, and to have a through hole serving as a first through hole, and a movable electrode serving as a vibratable third electrode formed on the sealing member to block up the through hole, and to be spaced from and opposed to the movable electrode.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 29, 2012
    Assignee: OKI Semiconductor Co., Ltd.
    Inventor: Yasushi Igarashi
  • Publication number: 20100213789
    Abstract: An electrostatic drive MEMS (Micro Electro Mechanical Systems) element includes a substrate; a fixed electrode disposed on the substrate; a movable electrode arranged to face the fixed electrode in a vertical direction and be movable toward the fixed electrode through an electrostatic force generated between the fixed electrode and the movable electrode; and an insulation film disposed on one of an upper surface of the fixed electrode and a lower surface of the movable electrode and formed of an insulation member containing a conductive fine particle.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 26, 2010
    Inventor: Yasushi IGARASHI
  • Patent number: 7666700
    Abstract: The present invention is an etching mask used for fabricating of the MEMS resonator including an oscillator which both edges are fixed to a base substance and vibrates to a vibrating direction, and an electrode which is fixed to a base substance by vibration is impossible in parallel for the oscillator, and is placed every one or more at the both sides of the oscillator. The etching mask includes a mask pattern 36 for oscillators which covers an oscillator formation scheduled region 34 on a conductive film 30 formed all over a sacrificial film which covers a region of the principal surface except both edges of the oscillator, and a mask pattern 40 for electrodes which covers an electrode formation scheduled region 38 on a conductive film.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: February 23, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Yasushi Igarashi
  • Publication number: 20090243737
    Abstract: A discharge electrode is provided on the opposite side of a fixed electrode with a beam portion being sandwiched therebetween. When the frequency of the MEMS oscillator is regulated by increasing the mass of a vibration element, the vibration element is used as a positive electrode and the discharge electrode as a negative electrode, and a direct current voltage is applied until an arc discharge occurs. When an arc discharge occurs between the vibration element and discharge electrode, an inert gas is ionized to become positive ions to collide against the discharge electrode to sputter or evaporate the material of the discharge electrode. A portion of discharged material from the discharge electrode adheres to the vibration element, therefore, the mass of the vibration element is increased to reduce a resonance frequency of the MEMS oscillator.
    Type: Application
    Filed: February 6, 2009
    Publication date: October 1, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Yasushi Igarashi
  • Publication number: 20090146227
    Abstract: A capacitive sensor according to the present invention includes a semiconductor substrate, a fixed electrode serving as a first electrode formed on a surface of or in the semiconductor substrate, a structure formed on the semiconductor substrate to have a vibratable second electrode that is formed to be spaced from and opposed to the semiconductor substrate and from the fixed electrode serving as the first electrode, a sealing member serving as a first sealing member formed on the semiconductor substrate to be spaced from the structure, to cover the structure, and to have a through hole serving as a first through hole, and a movable electrode serving as a vibratable third electrode formed on the sealing member to block up the through hole, and to be spaced from and opposed to the movable electrode.
    Type: Application
    Filed: November 25, 2008
    Publication date: June 11, 2009
    Applicant: OKI SEMICONDUCTOR CO., LTD.
    Inventor: Yasushi Igarashi
  • Publication number: 20080233673
    Abstract: The present invention is an etching mask used for fabricating of the MEMS resonator including an oscillator which both edges are fixed to a base substance and vibrates to a vibrating direction, and an electrode which is fixed to a base substance by vibration is impossible in parallel for the oscillator, and is placed every one or more at the both sides of the oscillator. The etching mask includes a mask pattern 36 for oscillators which covers an oscillator formation scheduled region 34 on a conductive film 30 formed all over a sacrificial film which covers a region of the principal surface except both edges of the oscillator, and a mask pattern 40 for electrodes which covers an electrode formation scheduled region 38 on a conductive film.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 25, 2008
    Applicant: OKI ELECTRIC INDUSTRY CO., LTD.
    Inventor: Yasushi Igarashi
  • Patent number: 7256088
    Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: August 14, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Igarashi
  • Patent number: 7120044
    Abstract: Data stored in a ferroelectric capacitor in a ferroelectric memory cell are read by applying a preliminary voltage to the ferroelectric capacitor to increase its polarization if a certain data value is stored, then applying a series of read voltages to produce a potential responsive to the stored data. The preliminary voltage may be applied either before or after one terminal of the ferroelectric capacitor is placed in a floating state, which is maintained while the series of read voltages is applied. Application of the preliminary voltage provides an increased reading margin if the ferroelectric capacitor has partially lost polarization while storing the certain data value, by restoring some of the lost polarization.
    Type: Grant
    Filed: July 2, 2004
    Date of Patent: October 10, 2006
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Igarashi
  • Patent number: 6936478
    Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: August 30, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kouichi Tani, Yasushi Igarashi
  • Publication number: 20050161724
    Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.
    Type: Application
    Filed: March 29, 2005
    Publication date: July 28, 2005
    Inventor: Yasushi Igarashi
  • Publication number: 20050139917
    Abstract: A semiconductor device has an anode impurity region and a cathode impurity region on a semiconductor substrate with a SOI (Silicon-On-Insulator) structure. An impurity region for voltage control is formed between the anode impurity region and the cathode impurity region.
    Type: Application
    Filed: May 19, 2004
    Publication date: June 30, 2005
    Inventor: Yasushi Igarashi
  • Patent number: 6911363
    Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: June 28, 2005
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Igarashi
  • Publication number: 20050033901
    Abstract: Data stored in a ferroelectric capacitor in a ferroelectric memory cell are read by applying a preliminary voltage to the ferroelectric capacitor to increase its polarization if a certain data value is stored, then applying a series of read voltages to produce a potential responsive to the stored data. The preliminary voltage may be applied either before or after one terminal of the ferroelectric capacitor is placed in a floating state, which is maintained while the series of read voltages is applied. Application of the preliminary voltage provides an increased reading margin if the ferroelectric capacitor has partially lost polarization while storing the certain data value, by restoring some of the lost polarization.
    Type: Application
    Filed: July 2, 2004
    Publication date: February 10, 2005
    Inventor: Yasushi Igarashi
  • Patent number: 6834006
    Abstract: Data stored in a ferroelectric capacitor in a ferroelectric memory cell are read by applying a preliminary voltage to the ferroelectric capacitor to increase its polarization if a certain data value is stored, then applying a series of read voltages to produce a potential responsive to the stored data. The preliminary voltage may be applied either before or after one terminal of the ferroelectric capacitor is placed in a floating state, which is maintained while the series of read voltages is applied. Application of the preliminary voltage provides an increased reading margin if the ferroelectric capacitor has partially lost polarization while storing the certain data value, by restoring some of the lost polarization.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: December 21, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Igarashi
  • Patent number: 6828189
    Abstract: A semiconductor device and a fabricating method thereof, capable of suppressing diffusion of hydrogen into a device and also capable of maintaining high performance are provided, while a passivation film is formed in a device whose performance is easily deteriorated by hydrogen diffusions. The semiconductor device is comprised of: a semiconductor substrate; a ferroelectric capacitor formed on the semiconductor substrate; a first interlayer film containing the ferroelectric capacitor; and a passivation film formed on the first interlayer film; in which a hydrogen diffusion preventing film is formed under the passivation film, and substantially adjacent to this passivation film. Also, the method for fabricating the semiconductor device is comprised of at least a step for forming a hydrogen diffusion preventing film under a passivation film and also substantially adjacent to this passivation film.
    Type: Grant
    Filed: March 27, 2002
    Date of Patent: December 7, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Igarashi
  • Patent number: 6710384
    Abstract: The wiring structure provided to the semiconductor memory device comprises a main wiring layer and barrier metal layer each established in the substrate and is connected to the lower electrode of a capacitive element. The main wiring layer and lower electrode are isolated from each other by a barrier metal layer acting as a material impermeable to oxygen; as a result, the main wiring layer is not easily oxidized.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: March 23, 2004
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Igarashi
  • Publication number: 20030222301
    Abstract: A semiconductor device of the present invention includes capacitors made up of a lower electrode, a capacitive insulation film made from metal oxide material, provided on one surface of a semiconductor substrate. An ozone TEOS film is provided on these capacitors, and a protective film for covering the upper surfaces of the capacitors is then provided on this ozone TEOS film. An interlay insulation film that is thicker than the ozone TEOS film is provided on the protective film for covering the upper surfaces of the capacitors. In this way, the present invention prevents degradation in film quality of the capacitive insulation film due to mutual reaction etc. As a result, it becomes possible to provide a capacitor using an insulating film made of a metal oxide as a capacitive insulation film, having a protective film for sufficiently preventing diffusion of H2, a semiconductor device having high reliability, and a method of manufacturing such a semiconductor device, are provided.
    Type: Application
    Filed: April 16, 2003
    Publication date: December 4, 2003
    Inventor: Yasushi Igarashi
  • Publication number: 20030201478
    Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.
    Type: Application
    Filed: May 6, 2003
    Publication date: October 30, 2003
    Inventors: Kouichi Tani, Yasushi Igarashi
  • Patent number: 6623985
    Abstract: A semiconductor device and method for manufacturing the same in which the semiconductor device includes a substrate; an MOS transistor formed on the substrate; an interlayer dielectric provided on at least a portion of the MOS transistor; a hydrogen occluding material which is an interstitial hydrogen occluding compound, which is provided on the interlayer dielectric, and which is employed as a wire by being disposed in the vicinity of the top of the MOS transistor; and a ferroelectric capacitor which has a height which is greater than that of the MOS transistor, wherein the hydrogen occluding material is placed between the MOS transistor and the ferroelectric capacitor.
    Type: Grant
    Filed: July 28, 2000
    Date of Patent: September 23, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Yasushi Igarashi
  • Patent number: 6600185
    Abstract: A ferroelectric capacitor has a top electrode, a bottom electrode, a ferroelectric body disposed between the top and bottom electrodes, and a dielectric lining disposed below the top electrode and above the bottom electrode, protecting the sides of the ferroelectric body. The ferroelectric body can be formed by chemical-mechanical polishing of a ferroelectric film. In a memory device, the capacitor is coupled to a transistor. The dielectric lining protects the ferroelectric body from etching damage during the fabrication process, obviating the need for repeated annealing to repair such damage, thereby avoiding the alteration of transistor characteristics that would be caused by such annealing.
    Type: Grant
    Filed: January 14, 2000
    Date of Patent: July 29, 2003
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Kouichi Tani, Yasushi Igarashi