Patents by Inventor Yasushi Iwata

Yasushi Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060104850
    Abstract: In a surface layer of an ultra-low carbon stainless steel comprising a seal function layer in the surface layer, an ion such as a nitrogen ion is implanted to form the seal function layer. Since the ultra-low carbon stainless steel comprising the seal function layer is excellent in elasticity, sealing properties, peelability and abrasion resistance, it can make a seal material which has been used unnecessary, and can realize all stainless-made products such as seal and joint system parts.
    Type: Application
    Filed: July 30, 2003
    Publication date: May 18, 2006
    Inventors: Yasushi Iwata, Akiyoshi Chayahara
  • Publication number: 20050061758
    Abstract: A storage apparatus is provided that comprises a display case part with an inside thereof being dividable into a plurality of zones, a supply duct that is connected to supply openings for supplying conditioning air for controlling environmental conditions to the plurality of zones respectively, and an exhaust duct that is connected to exhaust openings for taking in air from the plurality of zones. In this storage apparatus, conditioning air such as cold air or hot air is circulated in the respective zones, and the environmental conditions can be adjusted efficiently in zone basis. Therefore, in a storage apparatus equipped with an open-type display case part, it is possible to dispense with an air curtain covering the entire open side, so that a storage apparatus with a high storage capacity is provided.
    Type: Application
    Filed: December 27, 2002
    Publication date: March 24, 2005
    Inventors: Satoshi Nomura, Yuuichi Minamiyama, Ichiro Furihata, Kenji Kuno, Yasushi Iwata
  • Patent number: 6847261
    Abstract: A constant output signal can be achieved by controlling a gain variable amplifier 2 based on a level of an output signal which is derived by variably amplifying a receiving signal S1 (input signal). An AGC output signal S11 is detected by a detector circuit 3, then a detected voltage signal S7 is converted into a digital signal by an A/D converter 4 to output it to a CPU 5. Then, the CPU 5 generates a control signal S8 based on the detected voltage signal S7, then an A/D converter 6 converts the control signal S8 into the analogue signal, and then the signal is sent out to the gain variable amplifier 2 to execute gain control. At this time, an RSSI detector portion 9 detects an RSSI signal S10 corresponding to a transmitting signal level from the receiving signal S1, and then the CPU 5 sends out the control signal S8 stored at the time of preceding execution of the gain control when the RSSI signal S10 is reduced below a predetermined threshold value S12.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: January 25, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Publication number: 20040189383
    Abstract: A constant output signal can be achieved by controlling a gain variable amplifier 2 based on a level of an output signal which is derived by variably amplifying a receiving signal S1 (input signal). An AGC output signal S11 is detected by a detector circuit 3, then a detected voltage signal S7 is converted into a digital signal by an A/D converter 4 to output it to a CPU 5. Then, the CPU 5 generates a control signal S8 based on the detected voltage signal S7, then an A/D converter 6 converts the control signal S8 into the analogue signal, and then the signal is sent out to the gain variable amplifier 2 to execute gain control. At this time, an RSSI detector portion 9 detects an RSSI signal S10 corresponding to a transmitting signal level from the receiving signal S1, and then the CPU 5 sends out the control signal S8 stored at the time of preceding execution of the gain control when the RSSI signal S10 is reduced below a predetermined threshold value S12.
    Type: Application
    Filed: April 12, 2004
    Publication date: September 30, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Patent number: 6745016
    Abstract: A constant output signal can be achieved by controlling a gain variable amplifier 2 based on a level of an output signal which is derived by variably amplifying a receiving signal S1 (input signal). An AGC output signal S11 is detected by a detector circuit 3. Then, a CPU 5 generates a control signal S8 based on a detected voltage signal S7. An RSSI detector portion 9 detects an RSSI signal S10 corresponding to a transmitting signal level from the receiving signal S1. The transmitting signal level is compared to a preceding transmitting signal level. The control signal from a preceding execution of the gain control is output if the present control signal is lower than the preceding control signal and the present transmitting signal level is reduced below the preceding transmitting signal level.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: June 1, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Patent number: 6708025
    Abstract: At the power-on, a determination section (9) outputs a switch control signal (m) to a selector switch (7) to select the output of a sweep signal generator (6) which generates a voltage sweep signal (h) that increases from the minimum value to the maximum value of the gain control voltage range (p) at the same time, then provides the voltage sweep signal (h) to the variable gain amplifier (1), and calculates the difference (f) between the level detection value of an output signal (c) and a convergence value (e) and detects a sweep voltage value (j) obtained when (f)=0 and stores the sweep voltage value (j) into memory. After the sweep operation, the sweep voltage value (j) stored in memory is provided as a gain control signal (b) to the variable gain amplifier (1). Then the primary automatic gain control via the closed loop control system is started.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: March 16, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Publication number: 20030143968
    Abstract: A constant output signal can be achieved by controlling a gain variable amplifier 2 based on a level of an output signal which is derived by variably amplifying a receiving signal S1 (input signal). An AGC output signal S11 is detected by a detector circuit 3. Then, a CPU 5 generates a control signal S8 based on a detected voltage signal S7. An RSSI detector portion 9 detects an RSSI signal S10 corresponding to a transmitting signal level from the receiving signal S1. The transmitting signal level is compared to a preceding transmitting signal level. The control signal from a preceding execution of the gain control is output if the present control signal is lower than the preceding control signal and the present transmitting signal level is reduced below the preceding transmitting signal level.
    Type: Application
    Filed: February 4, 2003
    Publication date: July 31, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. a corporation of Japan
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Patent number: 6597898
    Abstract: A constant output signal can be achieved by controlling a gain variable amplifier 2 based on a level of an output signal which is derived by variably amplifying a receiving signal S1 (input signal). An AGC output signal S11 is detected by a detector circuit 3, then a detected voltage signal S7 is converted into a digital signal by an A/D converter 4 to output it to a CPU 5. Then, the CPU 5 generates a control signal S8 based on the detected voltage signal S7, then an A/D converter 6 converts the control signal S8 into the analogue signal, and then the signal is sent out to the gain variable amplifier 2 to execute gain control. At this time, an RSSI detector portion 9 detects an RSSI signal S10 corresponding to a transmitting signal level from the receiving signal S1, and then the CPU 5 sends out the control signal S8 stored at the time of preceding execution of the gain control when the RSSI signal S10 is reduced below a predetermined threshold value S12.
    Type: Grant
    Filed: January 6, 2000
    Date of Patent: July 22, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Patent number: 6577852
    Abstract: When an input signal S11 is variable-gain-amplified by a variable gain amplifier 1 to obtain a predetermined output signal S12, a variable gain control signal S15 is generated by a detecting circuit 2, an A/D converter 3, an adder 4, and a converting unit 5. Both a latch circuit 6 and an adder 7 calculate a difference between a variable gain control signal generated during a preceding control operation and a present variable gain control signal. When the difference result is equal to “0”, a counter 8 counts predetermined stable condition continued time, and thereafter outputs a non-operation setting signal S16. Also, the counter 8 sends out the variable gain control signal generated during the preceding control operation to the variable gain amplifier 1 so as to set the detecting circuit 2, the A/D converter 3, the adder 4, and the converting unit 5 into non-operation conditions thereof.
    Type: Grant
    Filed: July 5, 2000
    Date of Patent: June 10, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Publication number: 20010044287
    Abstract: At the power-on, a determination section (9) outputs a switch control signal (m) to a selector switch (7) to select the output of a sweep signal generator (6) which generates a voltage sweep signal (h) that increases from the minimum value to the maximum value of the gain control voltage range (p) at the same time, then provides the voltage sweep signal (h) to the variable gain amplifier (1), and calculates the difference (f) between the level detection value of an output signal (c) and a convergence value (e) and detects a sweep voltage value (j) obtained when (f)=0 and stores the sweep voltage value (j) into memory. After the sweep operation, the sweep voltage value (j) stored in memory is provided as a gain control signal (b) to the variable gain amplifier (1). Then the primary automatic gain control via the closed loop control system is started.
    Type: Application
    Filed: February 16, 2001
    Publication date: November 22, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasushi Iwata, Yasufumi Ichikawa
  • Patent number: 6275921
    Abstract: A data processing device includes an instruction storage memory which stores load instructions by eliminating NOP instructions for insertion into a load module of a VLIW computer. The data processing device also includes a device to expand the compressed load module automatically by a hardware circuit during instruction execution. The data processing device compresses and stores specific instruction code strings in memory with information indicating a form of compression and then restores the instruction code strings to an original format when read from memory according to the compression information. Information indicating an original storage position is attached to each instruction code, instruction code strings are stored in memory without specific instruction codes, and then restored to the original code strings when read from memory according to the storage position information.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: August 14, 2001
    Assignee: Fujitsu Limited
    Inventors: Yasushi Iwata, Akira Asato
  • Patent number: 6172446
    Abstract: A piezoelectric oscillator element (100) constituting a piezoelectric transformer is supported by lead frames (32, 34, 36). One of the ends of the lead frame (32) is welded to a primary side electrode (22) at a connection portion (31), and the other end is welded to a land (42). One of the ends of the lead frame (34) is welded to a primary side electrode (24) at a connection portion (33) and the other end is welded to a land (44). One of the ends of the lead frame (36) is welded to a secondary side electrode (26) at a connection portion (35) and the other end is welded to a land (46). The connection portions (31 and 33) are positioned at a node A of oscillation. Since the electrical and mechanical connection is achieved by the lead frames (32, 34, 36), the structure is simple, the thickness of the oscillator is easily reduced, and the oscillator is easily assembled.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: January 9, 2001
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Kouichi Kanayama, Shusaku Takagi, Mitsunobu Yoshida, Yasushi Iwata
  • Patent number: 6147439
    Abstract: A piezoelectric substrate supporting structure for piezoelectric transformer is provided which, in the supporting and fixing of a piezoelectric substrate on a base plate or in an outer trim case, does not inhibit the vibration of the piezoelectric substrate, exhibits high impact resistance and enables stable supporting, is free from performance deterioration and enables simultaneously and easily performing an electrode takeoff from the piezoelectric substrate. Further, a piezoelectric transformer including the above piezoelectric substrate supporting structure is provided.
    Type: Grant
    Filed: June 23, 1998
    Date of Patent: November 14, 2000
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Shusaku Takagi, Masamitsu Tanaka, Sigeru Bando, Tadao Sunahara, Katsuo Kono, Mitsunobu Yoshida, Yasushi Iwata
  • Patent number: 6038396
    Abstract: A compiling apparatus and method, and a recording medium, are used to facilitate assembly code programming of a VLIW computer system. An instruction of an intermediate code format, designated for each slot of the VLIW instruction, is divided corresponding to each slot and stored into a plurality of intermediate code files. The instructions of the intermediate code format stored in the intermediate code files are then read in serially to execute an instruction scheduling process, taking into account dependency between instructions. The serialized instructions of the intermediate code format are converted into parallel assembly code, and an object program of the parallel assembly code is output.
    Type: Grant
    Filed: March 17, 1998
    Date of Patent: March 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Yasushi Iwata, Akira Asato
  • Patent number: 5962849
    Abstract: In the time-of-flight mass spectrometer, the mass spectrometer with high resolution is provided which defines the initial position and the initial velocity of the charged particles and selects only the stable charged particles to measure.First, all of the charged particles Pe are accelerated to one direction in a homogeneous or spatially uniform electric field during a common finite period of time, and then all of the charged particles Pe are accelerated to the opposite direction of the former in a homogeneous or spatially uniform electric field during a common finite period of time and given the same momentum in the opposite direction of the former. Two kind of particle selection method can be adopted. Only the charged particles Pe passing through a predetermined position at a predetermined time are selected by the selector.
    Type: Grant
    Filed: March 25, 1997
    Date of Patent: October 5, 1999
    Assignee: Agency of Industrial Science & Technology
    Inventors: Naoaki Saito, Mitsumori Tanimoto, Kazuyoshi Koyama, Yasushi Iwata
  • Patent number: 5043598
    Abstract: A high voltage generating circuit which includes a switching circuit for switching a DC input, a fly-back transformer whose input coil is driven by pulses delivered from the switching actuation of the switching actuation of the circuit, a rectifier circuit for rectifying the fly-back voltage generated in the output coil of the fly-back transformer, a capacitor for smoothing the rectified output, and a voltage stabilizing circuit. A diode is electrically connected to one terminal of the output coil of the fly-back transformer on the low-voltage side thereof as compared with the ground, the diode being so determined as to position in the forward direction to the direction of rectification. The voltage stabilizing circuit is formed by a voltage sensing circuit for sensing a DC high voltage output, comparing it with a reference voltage applied from a reference voltage source and generating an output of a result of comparison and a control circuit connected between the anode of the diode and the ground terminal.
    Type: Grant
    Filed: September 15, 1989
    Date of Patent: August 27, 1991
    Assignee: TDK Corporation
    Inventors: Tsutomu Maeda, Kiyoshi Matsui, Michio Ishikawa, Takayuki Kanno, Yasushi Iwata