Patents by Inventor Yasushi Kinugasa

Yasushi Kinugasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6470035
    Abstract: A receiver receives a signal transmitted by a time-division multi-access method that divides one frame into a plurality of communication slots in conducting communication. In this receiver, a detection circuit detects whether a received RF signal is stronger than a predetermined level. The received RF signal is demodulated by a demodulation circuit. An oscillation circuit generates a clock that is used to decode the data obtained by demodulation. The data obtained by demodulation is stored in a memory in synchronism with a clock reproduced from the received signal, and is then retrieved from the memory in synchronism with the clock generated by the oscillation circuit. This eliminates jitters. After jitter elimination, the data is decoded by a processing circuit. The writing/reading operation against the memory is initialized in accordance with a result output from the detection circuit.
    Type: Grant
    Filed: March 2, 1999
    Date of Patent: October 22, 2002
    Assignee: Rohm Co., Ltd.
    Inventor: Yasushi Kinugasa
  • Patent number: 6426531
    Abstract: A semiconductor integrated circuit chip has a test pad and a mounting pad that are connected together by a conductor. The mounting pad is connected also to an internal circuit by way of a conductor. Near the test pad, protection diodes are provided, and, beside the test pad, supplied-voltage and ground-voltage application pads for the protection diodes are provided. Moreover, near the mounting pad, mount-assist pads are provided. During inspection, a supplied voltage and a ground voltage are supplied to the protection diodes from probes put on the supplied-voltage and ground-voltage application pads, and inspection is conducted with another probe put on the test pad. When this semiconductor chip is mounted on a semiconductor chip having a similar structure with a bump, the mounting pads and the mount-assist pads of the two semiconductor chips are short-circuited together so that the two semiconductor chips are mounted on each other.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: July 30, 2002
    Assignee: Rohm Co., Ltd.
    Inventor: Yasushi Kinugasa
  • Patent number: 5315136
    Abstract: Disclosed is a semiconductor integrated circuit in which four FETs forming a double balanced mixer are adapted to exhibit uniform operational characteristics so that the double balanced mixer can properly operate to prevent distorsion of electric signals. In the present semiconductor integrated circuit at least an interconnection line connecting source electrodes of two of the four FETs to a first source electrode terminal and a counterpart interconnection line connecting source electrodes of the other two FETs to a second source electrode terminal are made to have substantially the same electrical resistance.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: May 24, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Yasushi Kinugasa
  • Patent number: 5289057
    Abstract: A level shift circuit composed of two terminals which are different in potential level, at least two capacitors each incorporating a ferroelectric material and connected to each other in series between the two terminals, and output terminals each provided on one side of each of the capacitors, so that the output terminals are capable of outputting respective signals which are different in direct-current voltage level.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: February 22, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Yasushi Kinugasa