Patents by Inventor Yasushi Kohno

Yasushi Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5112836
    Abstract: Cyclic anthranilic acid carboxylic acid derivatives of the following formula, ##STR1## wherein R.sup.1 is hydrogen atom, carboxyl group, lower alkoxy carbonyl group having 1 to 3 carbon atoms, or phenyl group which may be substituted, r.sup.2 and R.sup.4 are each independently a hydrogen atom, lower alkyl group having 1 to 3 carbon atoms or benzyl group, R.sup.3 is a hydrogen atom, halogen atom, nitro group, amino group, cyano group, carbamoyl group, carboxyl group, lower alkanoylamino group having 1 to 4 carbon atoms, benzoylamino group, lower alkylsulfonylamino group having 1 to 3 carbon atoms or phenylsulfonylamino group which may be substituted by methyl group; the acid addition or alkali salts thereof, are useful as drugs treat autoimmune diseases, antirheumatic agents and therapeutic or prophylactic agents to treat metabolic bone diseases.
    Type: Grant
    Filed: June 15, 1990
    Date of Patent: May 12, 1992
    Assignee: Kyorin Pharmaceutical Co., Ltd.
    Inventors: Yasushi Kohno, Eisuke Kojima
  • Patent number: 4912395
    Abstract: A testable LSI chip incorporating memory blocks, such as RAM and ROM, and random logic circuitry, and a testing method thereof are disclosed. A front-stage peripheral logic circuit block and rear-stage peripheral logic circuit block connected to the input and output modes of a memory block are provided on their output side and input side, respectively, with the flip-flops in correspondence to the input and output nodes of the memory block. The flip-flops on the output side and flip-flops on the input side are each connected to form a shift register. In testing the front peripheral logic block, the test result is latched in the flip-flops on the output side and then the contents are shifted out for reading. In testing the rear-stage peripheral logic circuit block, a bit pattern for testing is shifted-in and latched in the flip-flops on the input side and then supplied to the rear-stage peripheral logic circuit block under test.
    Type: Grant
    Filed: June 24, 1988
    Date of Patent: March 27, 1990
    Assignees: Hitachi, Ltd., Hitachi Computer Engineering
    Inventors: Yoshio Sato, Toshifumi Ishii, Yasushi Kohno