Patents by Inventor Yasushi Kose

Yasushi Kose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6433646
    Abstract: In a microwave oscillation circuit using a dielectric resonator, a bias resistor for determining a bias voltage supplied to a base terminal of a transistor is located in the neighborhood of a connection point between a feedback circuit side stub for the dielectric resonator and the base terminal of the transistor. The bias resistor has a resistance which basically determines a bias voltage supplied to the base terminal of the transistor and which is enough to make high the impedance of a bias voltage supplying circuit including the bias resistor, viewed at the input terminal of the transistor. Thus, a stable oscillation can be maintained independently of variation in a load impedance.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: August 13, 2002
    Assignee: NEC Corporation
    Inventors: Yasushi Kose, Akihiro Ogisou
  • Publication number: 20010019293
    Abstract: In a microwave oscillation circuit using a dielectric resonator, a bias resistor for determining a bias voltage supplied to a base terminal of a transistor is located in the neighborhood of a connection point between a feedback circuit side stub for the dielectric resonator and the base terminal of the transistor. The bias resistor has a resistance which basically determines a bias voltage supplied to the base terminal of the transistor and which is enough to make high the impedance of a bias voltage supplying circuit including the bias resistor, viewed at the input terminal of the transistor. Thus, a stable oscillation can be maintained independently of variation in a load impedance.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 6, 2001
    Inventors: Yasushi Kose, Akihiro Ogisou
  • Patent number: 5852318
    Abstract: A semiconductor device includes: a plurality of first field effect transistors (FETs) having a gate formed on a main surface of a semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; a plurality of second FETs having a gate formed on the main surface of the semiconductor substrate, and a drain and a source formed in regions on both sides of the gate; and an electrically conductive layer that penetrates the main surface and a back surface of the semiconductor substrate in a region between the pair of FETs; wherein the first and second FETs that form the pair of FETs are disposed close to each other so that their drains are opposite to each other; wherein region widths of the first and second FETs in a direction of shorter sides of sources thereof are substantially identical with region widths of the first and second FETs in a direction of shorter sides of drains thereof; wherein all the drains of the first and second FETs are electrically connected to each other; where
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: December 22, 1998
    Assignee: NEC Corporation
    Inventors: Kiyoshi Chikamatsu, Toshiro Watanabe, Toshiaki Inoue, Yasushi Kose
  • Patent number: 5477085
    Abstract: The present invention provides a bonding structure between a dielectric substrate made of a dielectric material and a packaging substrate made of a heat conductive material involved in microwave integrated circuits. Both the dielectric and heat conductive materials have different coefficients of thermal expansions. The dielectric substrate has a top surface formed thereon with a top metallization pattern constituting impedance matching circuits and a bottom surface being bonded through a soldering agent to the packaging substrate. The bottom surface of the dielectric substrate has a bottom metallization pattern being selectively formed in a predetermined area thereon so that the soldering agent is applied only on the bottom metallization pattern to bond the dielectric and packaging substrates with each other. The bottom metallization pattern may be the same as the top metallization pattern.
    Type: Grant
    Filed: November 28, 1994
    Date of Patent: December 19, 1995
    Assignee: NEC Corporation
    Inventor: Yasushi Kose