Abstract: The present invention provides an aluminium titanate ceramic composed of, as main crystalline phases, 60-85% of an aluminum titanate phase, 10-25% of a rutile phase, 2-10% of a corundum phase and 2-10% of a mullite phase, wherein the amount of vitreous phase is 5% or less. The aluminum titanate ceramic is superior in both heat cycle durability and casted property.

Abstract: An aluminum titanate ceramic has as main crystalline phases, a crystalline phase of aluminum titanate and a solid solution thereof, a crystalline phase of mullite and a crystalline phase of rare earth titanate represented by RE.sub.2 Ti.sub.2 O.sub.7 (RE represents Y, Yb, Er, Dy, Ho, Tm or Lu). The aluminum titanate ceramic is superior in casting property and has high heat cycle durability.

Abstract: A method of processing original still picture data representing an original still image and stored in a video memory and storing processed still picture data representing a processed still image in a predetermined location of the video memory comprising the steps of setting an XY orthogonal coordinate system on the video memory, setting a reference line parallel to one of the X and Y axes of the orthogonal coordinate system and passing through a point of intersection of lines, each of which connects corresponding pixels of the original and processed still images, moving multiples the pixel data on a line of the original still image parallel to the reference line and furthest from the reference line to addresses of the video memory forming a line of the processed still image, and repeating the preceding step for pixel data on lines of the still image parallel to the reference line and second furthest from the reference line and succeeding lines, to thereby store the processed still picture data representing th

Abstract: A still picture signal editing or processing apparatus having a still picture signal source for generating a still picture signal, an analog-to-digital converter for converting the still picture signal into a digitized still picture signal, first and second main field memories, an auxiliary field memory, a signal processer for processing a still picture signal, a display for displaying a still picture, a selector for supplying a signal selectively read out from the first and second main field memories to the display, and a memory controller for controlling read and write operations of the first and second main field memories and auxiliary field memory, thereby a digitized still picture signal from the analog-to-digital converter is supplied to the first main field memory, the digitized still picture signal is read out from the first main field memory, compressed by 1/n in data amount and is separated into first and second compressed signals by the signal processer, the first and second compressed signals are

Abstract: An apparatus for scrolling the display of images obtained from a plurality of data units, each having pattern signals representing a plurality of horizontal lines and a corresponding color signal includes a video display having a plurality of horizontal display lines, a first memory for storing the pattern signals formed with first addresses corresponding to the plurality of horizontal display lines and a first buffer area for temporarily storing received pattern signals, a second memory for storing the color signal formed with second addresses corresponding to the numbers of the data units and a second buffer area for temporarily storing a received color signal, the pattern signals and a corresponding color signal being stored in the first and second buffer areas, respectively.

Abstract: According to this invention, there are provided a plurality of memories in which predetermined data are written and a plurality of gates. Parity check bits are grouped into a plurality of groups in response to the bit number of the addresses of the memories. Of the grouped parity checkbits, the parity checkbits corresponding to the addresses of the memories are supplied to the addresses and the outputs of the memories are supplied to the gates so as to decode the parity check bits, whereby a threshold value is identified on the basis of the outputs of the gates.