Patents by Inventor Yasushi Ogata

Yasushi Ogata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12136640
    Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: November 5, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Keiichi Nakazawa, Koichiro Zaitsu, Nobutoshi Fujii, Yohei Hiura, Shigetaka Mori, Shintaro Okamoto, Keiji Ohshima, Shuji Manda, Junpei Yamamoto, Yui Yuga, Shinichi Miyake, Tomoki Kambe, Ryo Ogata, Tatsuki Miyaji, Shinji Nakagawa, Hirofumi Yamashita, Yasushi Hamamoto, Naohiko Kimizuka
  • Patent number: 8860899
    Abstract: A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between a conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: October 14, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 8531619
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with the first insulating film serving as a dielectric.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: September 10, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata
  • Patent number: 8497508
    Abstract: A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: July 30, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki
  • Patent number: 8384084
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: February 26, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Publication number: 20130001581
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with the first insulating film serving as a dielectric.
    Type: Application
    Filed: August 16, 2012
    Publication date: January 3, 2013
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi OHTANI, Yasushi OGATA
  • Publication number: 20120286280
    Abstract: A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between a conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching.
    Type: Application
    Filed: May 18, 2012
    Publication date: November 15, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 8248551
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large.
    Type: Grant
    Filed: May 19, 2011
    Date of Patent: August 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata
  • Publication number: 20120199986
    Abstract: A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps.
    Type: Application
    Filed: April 18, 2012
    Publication date: August 9, 2012
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki
  • Patent number: 8218100
    Abstract: An conductive coating serves as a light shield film and is kept at a give voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 8168975
    Abstract: A wiring line is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively without increasing the number of manufacturing steps.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: May 1, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki
  • Patent number: 8154676
    Abstract: An conductive coating serves as a light shield film and is kept at a give voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: April 10, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Publication number: 20110215327
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large.
    Type: Application
    Filed: May 19, 2011
    Publication date: September 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi OHTANI, Yasushi OGATA
  • Publication number: 20110147758
    Abstract: An conductive coating serves as a light shield film and is kept at a give voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Application
    Filed: February 25, 2011
    Publication date: June 23, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Patent number: 7948571
    Abstract: A first insulating thin film having a large dielectric constant such as a silicon nitride film is formed so as to cover a source line and a metal wiring that is in the same layer as the source line. A second insulating film that is high in flatness is formed on the first insulating film. An opening is formed in the second insulating film by etching the second insulating film, to selectively expose the first insulating film. A conductive film to serve as a light-interruptive film is formed on the second insulating film and in the opening, whereby an auxiliary capacitor of the pixel is formed between the conductive film and the metal wiring with first the insulating film serving as a dielectric. The effective aperture ratio can be increased by forming the auxiliary capacitor in a selected region where the influences of alignment disorder of liquid crystal molecules, i.e., disclination, are large.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: May 24, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata
  • Patent number: 7928438
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Grant
    Filed: November 19, 2007
    Date of Patent: April 19, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Toru Mitsuki, Akiharu Miyanaga, Yasushi Ogata
  • Patent number: 7898605
    Abstract: An conductive coating serves as a light shield film and is kept at a given voltage. A metal interconnection is located in the same layer as a source line and connected to the drain of a thin-film transistor. An interlayer insulating film is constituted of at least lower and upper insulating layers and formed between the conductive coating and the source line. According to one aspect of the invention, an auxiliary capacitor is formed by the metal interconnection and the conductive coating serving as both electrodes and at least the lower insulating layer film serving as a dielectric. The auxiliary capacitor is formed in a region of the interlayer insulating film in which the upper insulating layer has been removed by etching. According to another aspect of the invention, the conductive coating has a portion that is in contact with the lower insulating layer in a region where the conductive coating coextends with the metal interconnection.
    Type: Grant
    Filed: July 7, 2008
    Date of Patent: March 1, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisashi Ohtani, Yasushi Ogata, Yoshiharu Hirakata
  • Publication number: 20100295046
    Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.
    Type: Application
    Filed: August 4, 2010
    Publication date: November 25, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Hisashi OHTANI, Toru MITSUKI, Akiharu MIYANAGA, Yasushi OGATA
  • Patent number: 7791576
    Abstract: To provide a constitution capable of reducing production cost in a semiconductor device for display of a type integrally formed with a drive circuit with a digital signal as an input signal and a pixel matrix unit, a signal dividing circuit is formed on a substrate where drive circuits and a pixel matrix unit are to be formed simultaneously with the drive circuits and the pixel matrix unit in view of fabrication steps by which fabrication steps of the signal dividing circuit per se and steps required for connecting the signal dividing circuit to wirings on the substrate can be dispensed with without adding further steps.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: September 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd
    Inventors: Jun Koyama, Mitsuaki Osame, Yasushi Ogata
  • Patent number: RE43782
    Abstract: A wiring line to which a high-frequency signal is applied is electrically connected in parallel to an auxiliary wiring line via a plurality of contact holes. The contact holes are formed through an interlayer insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively and waveform rounding of an applied high-frequency signal can be reduced without increasing the number of manufacturing steps.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: November 6, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Jun Koyama, Hisashi Ohtani, Yasushi Ogata, Shunpei Yamazaki