Patents by Inventor Yasushi Oka

Yasushi Oka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220308402
    Abstract: According to one embodiment, a liquid crystal optical element includes a substrate, a plurality of structures, a first liquid crystal layer including a plurality of liquid crystal molecules having alignment directions fixed, and a second liquid crystal layer including a plurality of liquid crystal molecules having alignment directions fixed. In an area overlapping a groove, a first director of the first liquid crystal layer extends along the groove, and a second director of the second liquid crystal layer is uniformly aligned with the first director of the second surface side, on the third surface side, and turns in planar view.
    Type: Application
    Filed: March 21, 2022
    Publication date: September 29, 2022
    Applicant: Japan Display Inc.
    Inventors: Shinichiro OKA, Yasushi TOMIOKA, Koichi IGETA, Junji KOBASHI
  • Publication number: 20220299825
    Abstract: According to one embodiment, a liquid crystal element includes a transparent substrate including a first main surface, a plurality of structures disposed on the first main surface and arranged along one direction, an alignment film disposed on a surface of each of the structures and a liquid crystal layer containing a cholesteric liquid crystal and in contact with the alignment film, and the helical axis of the cholesteric liquid crystal is inclined with respect to the first main surface, each of the plurality of structures includes a first surface inclined with respect to the first main surface, in the plurality of structures, the first surfaces are parallel to each other, and the alignment film is interposed between the first surface and the liquid crystal layer.
    Type: Application
    Filed: March 16, 2022
    Publication date: September 22, 2022
    Applicant: Japan Display Inc.
    Inventors: Junji KOBASHI, Shinichiro OKA, Yasushi TOMIOKA, Koichi IGETA
  • Patent number: 11390037
    Abstract: Regarding a laser welded body in which a laser transmissive/absorptive molding member containing a PBT-based material and a laser absorptive molding member containing a PBT-based material are integrated with each other by laser welding, the following laser welded body is proposed as a laser welded body in which a bond strength can be further increased. A laser welded body having a structure in which a member I and a member II are integrally bonded to each other, the member I contains 0.0005 to 5.0 parts by mass, with respect to 100 parts by mass of a polyester-based resin A, of a laser transmissive/absorptive coloring material capable of transmitting and absorbing laser beam, and the polyester-based resin A contains at least a polybutylene terephthalate copolymer resin, the member II contains 0.15 to 10.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: July 19, 2022
    Assignee: Mitsubishi Engineering-Plastics Corporation
    Inventors: Akihiro Oka, Yuki Hiwatashi, Yasushi Yamanaka
  • Publication number: 20140140133
    Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Hideaki YAMAKOSHI, Yasushi OKA, Daisuke OKADA
  • Patent number: 8351255
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: January 8, 2013
    Assignee: Renesas Electronics COrporation
    Inventors: Kazuyoshi Shiba, Yasushi Oka
  • Patent number: 8325524
    Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: December 4, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Oka, Tadashi Omae, Takesada Akiba
  • Publication number: 20120223376
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Application
    Filed: May 11, 2012
    Publication date: September 6, 2012
    Inventors: Kazuyoshi Shiba, Yasushi Oka
  • Patent number: 8189377
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: May 29, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Shiba, Yasushi Oka
  • Publication number: 20110233639
    Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.
    Type: Application
    Filed: March 13, 2011
    Publication date: September 29, 2011
    Inventors: Hideaki YAMAKOSHI, Yasushi OKA, Daisuke OKADA
  • Publication number: 20110147819
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Application
    Filed: February 24, 2011
    Publication date: June 23, 2011
    Inventors: KAZUYOSHI SHIBA, YASUSHI OKA
  • Patent number: 7940561
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Grant
    Filed: October 21, 2009
    Date of Patent: May 10, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kazuyoshi Shiba, Yasushi Oka
  • Publication number: 20110024814
    Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
    Type: Application
    Filed: October 13, 2010
    Publication date: February 3, 2011
    Inventors: Yasushi OKA, Tadashi Omae, Takesada Akiba
  • Patent number: 7839683
    Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 23, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Yasushi Oka, Tadashi Omae, Takesada Akiba
  • Publication number: 20100038693
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Application
    Filed: October 21, 2009
    Publication date: February 18, 2010
    Inventors: Kazuyoshi SHIBA, Yasushi OKA
  • Patent number: 7652917
    Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: January 26, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasushi Oka, Kazuyoshi Shiba
  • Patent number: 7639541
    Abstract: A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: December 29, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyoshi Shiba, Yasushi Oka
  • Patent number: 7623371
    Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kazuyoshi Shiba, Yasushi Oka
  • Publication number: 20090154253
    Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.
    Type: Application
    Filed: November 13, 2008
    Publication date: June 18, 2009
    Inventors: Kazuyoshi SHIBA, Yasuhiro Taniguchi, Yasushi Oka
  • Publication number: 20090080257
    Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
    Type: Application
    Filed: September 18, 2008
    Publication date: March 26, 2009
    Inventors: YASUSHI OKA, Tadashi Omae, Takesada Akiba
  • Publication number: 20090059677
    Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.
    Type: Application
    Filed: October 29, 2008
    Publication date: March 5, 2009
    Inventors: YASUSHI OKA, Kazuyoshi Shiba