Abstract: A semiconductor memory includes: a plurality of memory cell transistors: a plurality of first bit lines; a plurality of second bit lines; a first transistor provided between a charging section for charging at least one of the plurality of first bit lines and the plurality of memory cell transistors; and a second transistor provided between a discharging section for discharging at least one of the plurality of second bit lines and the plurality of memory cell transistors, wherein one of a source region and a drain region of each of the plurality of memory cell transistors is formed as a part of one of the plurality of first bit lines, and the other of a source region and a drain region is formed as a part of one of the plurality of second bit lines; an ON/OFF state of the first transistor is controlled based on a first signal; an ON/OFF state of the second transistor is controlled based on a second signal; and the second signal is provided to the second transistor at a time which is delayed for a predetermined

Abstract: A PROM built-in micro computer has a semiconducting nonvolatile memory which can be written into electrically, and has a micro computer. It detects a semiconducting nonvolatile memory cell whose readout current is less than or equal to a constant value at a time of data comparison after a writing operation. The PROM built-in micro computer is adapted to prevent a readout error which may result from a fluctuation of temperature or supply voltage. This may be done by changing a reference potential at the time of a data comparison, by changing the sensitivity of a sense amplifier, or by changing a readout current or a threshold value of the PROM cell.

Abstract: An integrated circuit device having a processing unit (3) with a plurality of input terminals (I1-In) and adapted to cancel its stand-by mode when a pulse-like control signal (A) having a predetermined duration is received by one of the input terminals. The integrated circuit device includes a plurality of external terminals (T1-Tn) for receiving signals and a plurality of control signal generating circuits (C1-Cn) each having an input connected to a corresponding one of the external terminals. Each control signal generating circuit (C1-Cn) has an output terminal connected to a corresponding one of the input terminals of the processing unit (3). Each of the control signal generating circuits has a D flip-flop (4) for, on receiving a pulse signal (R) for canceling the stand-by mode from the processing unit (3), elongating a duration of the pulse signal to a predetermined duration.