Patents by Inventor Yasushi Okura

Yasushi Okura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210028085
    Abstract: In a semiconductor device, a first protection film covers an end portion of a first metal layer disposed on a semiconductor substrate, and has a first opening above the first metal layer. A second metal layer is disposed on the first metal layer in the first opening. An oxidation inhibition layer is disposed on the second metal layer in the first opening. A second protection film has a second opening and covers an end portion of the oxidation inhibition layer and the first protection film. The second protection film has an opening peripheral portion on a periphery of the second opening, and covers the end portion of the oxidation inhibition layer. An adhesion portion adheres to a portion of a lower surface of the opening peripheral portion. The adhesion portion has a higher adhesive strength with the second protection film than the oxidation inhibition layer.
    Type: Application
    Filed: October 15, 2020
    Publication date: January 28, 2021
    Inventor: Yasushi OKURA
  • Publication number: 20190097030
    Abstract: A plug electrode is subject to etch back to remain in a contact hole and expose a barrier metal on a top surface of an interlayer insulating film. The barrier metal is subject to etch back, exposing the top surface of the interlayer insulating film. Remaining element structures are formed. After lifetime is controlled by irradiation of helium or an electron beam, hydrogen annealing is performed. During the hydrogen annealing, the barrier metal is not present on the interlayer insulating film covering a gate electrode, enabling hydrogen atoms to reach a mesa part, whereby lattice defects generated in the mesa part by the irradiation of helium or an electron beam are recovered, recovering the gate threshold voltage. Thus, predetermined characteristics of a semiconductor device having a structure where a plug electrode is provided in a contact hole, via barrier metal are easily and stably obtained when lifetime control is performed.
    Type: Application
    Filed: November 29, 2018
    Publication date: March 28, 2019
    Applicants: FUJI ELECTRIC CO., LTD., DENSO CORPORATION
    Inventors: Hiroshi Miyata, Seiji Noguchi, Souichi Yoshida, Hiromitsu Tanabe, Kenji Kouno, Yasushi Okura
  • Patent number: 8076718
    Abstract: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: December 13, 2011
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
  • Patent number: 7586151
    Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: September 8, 2009
    Assignees: Toyota Jidosha Kabushiki Kaisha, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
  • Patent number: 7470953
    Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: December 30, 2008
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura
  • Publication number: 20080087951
    Abstract: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.
    Type: Application
    Filed: September 28, 2005
    Publication date: April 17, 2008
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi, Yasushi Okura, Akira Kuroyanagi, Norihiko Tokura
  • Publication number: 20070241394
    Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of terminal trench 62.
    Type: Application
    Filed: May 11, 2005
    Publication date: October 18, 2007
    Inventors: Hidefumi Takaya, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
  • Publication number: 20060289928
    Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.
    Type: Application
    Filed: October 6, 2004
    Publication date: December 28, 2006
    Inventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura
  • Patent number: 6803667
    Abstract: A semiconductor device comprises a semiconductor element, a heat sink soldered to one surface of the semiconductor element, and a heat sink soldered to an opposite surface of the semiconductor element. The semiconductor element is provided with a wiring layer. The wiring layer is covered with an insulating protective film. The protective film is an organic film. The thickness of the wiring layer and that of the protective film are assumed to be t1 and t2, respectively. The wiring layer and the protective film are formed so as to establish a relationship of t1<t2. An elastic modulus of the protective film at room temperature is adjusted to 1.0-5.0 GPa and a thermal expansion coefficient of the protective film is adjusted to 35-65×10−6/° C. Even under a thermal stress the semiconductor device can diminish a short-circuit defect of the wiring layer.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: October 12, 2004
    Assignee: Denso Corporation
    Inventors: Yasushi Okura, Kuniaki Mamitsu, Naohiko Hirano
  • Publication number: 20030052400
    Abstract: A semiconductor device comprises a semiconductor element, a heat sink soldered to one surface of the semiconductor element, and a heat sink soldered to an opposite surface of the semiconductor element. The semiconductor element is provided with a wiring layer. The wiring layer is covered with an insulating protective film. The protective film is an organic film. The thickness of the wiring layer and that of the protective film are assumed to be t1 and t2, respectively. The wiring layer and the protective film are formed so as to establish a relationship of t1<t2. An elastic modulus of the protective film at room temperature is adjusted to 1.0-5.0 GPa and a thermal expansion coefficient of the protective film is adjusted to 35-65×10−6/°C. Even under a thermal stress the semiconductor device can diminish a short-circuit defect of the wiring layer.
    Type: Application
    Filed: August 5, 2002
    Publication date: March 20, 2003
    Inventors: Yasushi Okura, Kuniaki Mamitsu, Naohiko Hirano