Abstract: A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate electrode and a sufficiently thin shallow trench isolation (STI) is formed between adjacent gate electrodes. The drain current characteristics can be improved.

Abstract: Provided is a fabrication method of a semiconductor integrated circuit device, which comprises preparing a first mask having a plurality of openings formed in a halftone film which has been deposited over a mask substrate and has a function of reversing the phase of a transmitted light; preparing over said first mask a second mask which is made of a resist film capable of blocking an exposure light and has a resist pattern formed to expose desired opening patterns, among said plurality of opening patterns of said first mask, and a part of said halftone film around said desired opening patterns and to cover the other opening patterns; and transferring the desired patterns onto a photoresist film over a wafer by reduction projection exposure treatment with said second mask. According to the present invention, TAT and in turn, the delivery time of the semiconductor integrated circuit device can be shortened.

Abstract: A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate electrode and a sufficiently thin STI is formed between adjacent gate electrodes. The drain current characteristics can be improved.