Patents by Inventor Yasushi Takemori

Yasushi Takemori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9195553
    Abstract: The redundant system includes a redundant server of a first system and a redundant server of a second system. The redundant servers of the first system and the second system operate in lockstep. When a failure occurs in the redundant server of the second system, the redundant server of the first system separates the redundant server of the second system in which the failure has occurred and continues the operation, and then prepares for restoration to a duplexed operation with a configuration in which the failed part is fallen back. When the preparation is completed, both redundant servers of the first system and the second system start a lockstep operation from initialization processing by synchronous reset, and resume the duplexed operation with the configuration in which the failed part is fallen back.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: November 24, 2015
    Assignee: NEC CORPORATION
    Inventor: Yasushi Takemori
  • Publication number: 20130262917
    Abstract: The redundant system includes a redundant server of a first system and a redundant server of a second system. The redundant servers of the first system and the second system operate in lockstep. When a failure occurs in the redundant server of the second system, the redundant server of the first system separates the redundant server of the second system in which the failure has occurred and continues the operation, and then prepares for restoration to a duplexed operation with a configuration in which the failed part is fallen back. When the preparation is completed, both redundant servers of the first system and the second system start a lockstep operation from initialization processing by synchronous reset, and resume the duplexed operation with the configuration in which the failed part is fallen back.
    Type: Application
    Filed: March 14, 2013
    Publication date: October 3, 2013
    Applicant: NEC Corporation
    Inventor: Yasushi TAKEMORI
  • Patent number: 7552359
    Abstract: A computer system includes a plurality of systems configured to be connected to each other by links and to operate synchronously each other. Each of said plurality of systems includes a fault tolerant controller, a CPU, a baseboard management controller and a plurality of hardware modules. The CPU is connected with the fault tolerant controller. The baseboard management controller is connected with the fault tolerant controller. The plurality of hardware modules is connected with the fault tolerant controller. When receiving a trouble which occurs in any of the plurality of systems, the fault tolerant controller outputs an interrupt regarding the trouble to at least one of the CPU and the baseboard management controller predetermined correspondingly to the trouble.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: June 23, 2009
    Assignee: NEC Corporation
    Inventor: Yasushi Takemori
  • Publication number: 20060150009
    Abstract: A computer system includes a plurality of systems configured to be connected to each other by links and to operate synchronously each other. Each of said plurality of systems includes a fault tolerant controller, a CPU, a baseboard management controller and a plurality of hardware modules. The CPU is connected with the fault tolerant controller. The baseboard management controller is connected with the fault tolerant controller. The plurality of hardware modules is connected with the fault tolerant controller. When receiving a trouble which occurs in any of the plurality of systems, the fault tolerant controller outputs an interrupt regarding the trouble to at least one of the CPU and the baseboard management controller predetermined correspondingly to the trouble.
    Type: Application
    Filed: December 20, 2005
    Publication date: July 6, 2006
    Inventor: Yasushi Takemori
  • Publication number: 20060136641
    Abstract: A context save method, an information processor and an interrupt generator for restoring, after a reset of a CPU, CPU context information such as the interrupt acceptance state of the CPU before the CPU reset. An interrupt controller stores CPU context information set in a CPU in a memory before resetting the CPU. After the reset of the CPU, the interrupt controller reads out the CPU context information stored in the memory. The interrupt controller feeds interrupt acceptance information contained in the CPU context information to the interrupt generator. The interrupt generator generates an interrupt corresponding to the input information. Besides, the interrupt controller sets the CPU context information except for the interrupt acceptance information in the CPU.
    Type: Application
    Filed: December 15, 2005
    Publication date: June 22, 2006
    Inventor: Yasushi Takemori