Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

Abstract: The present technology relates to a solid-state imaging device and an electronic device that can expand a dynamic range in a pixel having a high-sensitivity pixel and a low-sensitivity pixel. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is arranged in a two-dimensional manner, in which the pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit having lower sensitivity than the first photoelectric conversion unit, and a size of the second photoelectric conversion unit in an optical axis direction in which light enters is smaller than a size of the first photoelectric conversion unit in the optical axis direction. The present technology can be applied to a backside-illumination CMOS image sensor, for example.

Abstract: Image quality is improved. In an image pickup element, an interval between adjacent light receiving elements on a light receiving surface is changed depending on a position on the light receiving surface. Further, the image pickup element is manufactured by a method of manufacturing the image pickup element including layering photodiodes by repeatedly performing a silicon epitaxial process and an ion injection process. Further, the image pickup element is manufactured by the method of manufacturing the image pickup element including changing an interval between the photodiodes adjacent on the light receiving surface of the image pickup element in each layer depending on a position on the light receiving surface in addition to the layering thereof.

Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus which allow reduction of optical crosstalk. In an example of FIG. 5B, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. In an example of FIG. 5C, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. The present disclosure can be applied to a CMOS solid-state imaging device used for an imaging apparatus such as a camera, for example.

Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

Abstract: The present technology relates to a solid-state imaging device and an electronic device that can expand a dynamic range in a pixel having a high-sensitivity pixel and a low-sensitivity pixel. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is arranged in a two-dimensional manner, in which the pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit having lower sensitivity than the first photoelectric conversion unit, and a size of the second photoelectric conversion unit in an optical axis direction in which light enters is smaller than a size of the first photoelectric conversion unit in the optical axis direction. The present technology can be applied to a backside-illumination CMOS image sensor, for example.

Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.

Abstract: The present disclosure relates to a solid-state imaging device and an electronic apparatus which allow reduction of optical crosstalk. In an example of FIG. 5B, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. In an example of FIG. 5C, a charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. By placing the charge storage unit (capacitance element) formed in the substrate in the foregoing manner between PDs which are first photoelectric conversion units, it is possible to allow the capacitance element to function as a shield pair against crosstalk between the PDs in a unit pixel.

Abstract: Provided is a solid-state imaging device and an electronic device that can expand a dynamic range in a pixel having a high-sensitivity pixel and a low-sensitivity pixel. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is arranged in a two-dimensional manner, in which the pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit having lower sensitivity than the first photoelectric conversion unit, and a size of the second photoelectric conversion unit in an optical axis direction in which light enters is smaller than a size of the first photoelectric conversion unit in the optical axis direction.

Abstract: Provided is a solid-state imaging device and an electronic device that can expand a dynamic range in a pixel having a high-sensitivity pixel and a low-sensitivity pixel. The solid-state imaging device includes a pixel array unit in which a plurality of pixels is arranged in a two-dimensional manner, in which the pixel includes a first photoelectric conversion unit and a second photoelectric conversion unit having lower sensitivity than the first photoelectric conversion unit, and a size of the second photoelectric conversion unit in an optical axis direction in which light enters is smaller than a size of the first photoelectric conversion unit in the optical axis direction.

Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

Abstract: Provided are a solid-state imaging device and an electronic apparatus that include a charge storage unit. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a surface of the hole, and an insulating film and an upper electrode are formed so as to fill the hole. The charge storage unit is formed by a method in which a hole is bored in a substrate, a diffusion layer is formed in a half (one side) of a surface of the hole, and an insulating film and an upper electrode are formed so as to the hole.

Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.

Abstract: In an image pickup element, an interval between adjacent light receiving elements on a light receiving surface is changed depending on a position on the light receiving surface. Further, the image pickup element is manufactured by a method of manufacturing the image pickup element including layering photodiodes by repeatedly performing a silicon epitaxial process and an ion injection process. Further, the image pickup element is manufactured by the method of manufacturing the image pickup element including changing an interval between the photodiodes adjacent on the light receiving surface of the image pickup element in each layer depending on a position on the light receiving surface in addition to the layering thereof.

Abstract: Image quality is improved. In an image pickup element, an interval between adjacent light receiving elements on a light receiving surface is changed depending on a position on the light receiving surface. Further, the image pickup element is manufactured by a method of manufacturing the image pickup element including layering photodiodes by repeatedly performing a silicon epitaxial process and an ion injection process. Further, the image pickup element is manufactured by the method of manufacturing the image pickup element including changing an interval between the photodiodes adjacent on the light receiving surface of the image pickup element in each layer depending on a position on the light receiving surface in addition to the layering thereof.

Abstract: A semiconductor device including, in cross section, a semiconductor substrate; a gate insulating film on the semiconductor substrate; a gate electrode on the gate insulating film, the gate electrode including a metal, a side wall insulating film at opposite sides of the gate electrode, the side wall insulating film contacting the substrate; a stress applying film at the opposite sides of the gate electrode and over at least a portion of the semiconductor substrate, at least portion of the side wall insulating film being between the gate insulating film and the stress applying film and in contact with both of them; source/drain regions in the semiconductor substrate at the opposite sides of the gate electrode, and silicide regions at surfaces of the source/drain regions at the opposite sides of the gate electrode, the silicide regions being between the source/drain regions and the stress applying layer and in contact with the stress applying layer.