Abstract: A processing system includes a receiving circuit 1 for receiving an input signal from an externally connected sensor, an expected signal generating circuit 4 for automatically generating a teaching signal for use in the learning circuit 5, a learning circuit 5 for calculating a weight value, a bias value, and the like of the neural network model to form an expected signal from the teaching signal generated by the expected signal generating circuit 4 and the signal from the receiving circuit 1, an inference circuit 2 for performing signal processing based on a learned model of the neural network model generated by the learning circuit 5, and a validity verification circuit 3? for performing similarity calculation between an output signal of the inference circuit 2 and an expected signal for comparison.

Abstract: A processing system includes a receiving circuit 1 for receiving an input signal from an externally connected sensor, an expected signal generating circuit 4 for automatically generating a teaching signal for use in the learning circuit 5, a learning circuit 5 for calculating a weight value, a bias value, and the like of the neural network model to form an expected signal from the teaching signal generated by the expected signal generating circuit 4 and the signal from the receiving circuit 1, an inference circuit 2 for performing signal processing based on a learned model of the neural network model generated by the learning circuit 5, and a validity verification circuit 3? for performing similarity calculation between an output signal of the inference circuit 2 and an expected signal for comparison.

Abstract: Error occurrence is predicted before the error occurs. Included are: a clock regeneration circuit (11) that regenerates, from a data input signal (Din), a clock signal (CK1) related to the data input signal (Din); a sampling clock generation circuit (12) that generates one or more sampling clock signals (CK2 and CK3) that are synchronous with the regenerated signal (CK1) and have a constant phase difference with respect to the regenerated clock signal (CK1); a sample and hold circuit (13) that samples and holds the data input signal (Din) according to the one or more sampling clock signals (CK2 and CK3) and the regenerated clock signal (CK1) respectively; and an error determination circuit (14) that outputs an error prediction signal (Ep) in a case where logical values of respective sampling results of the sample and hold circuit (13) are not all identical.

Abstract: A clock signal extracting circuit extracting a clock signal from N-pieces of data bit signals, where said N is an integer of two or more, including N-pieces of phase comparators, each of which compares a phase of each of the data bit signals with a phase of an extracted clock signal and generates a up-signal and a down-signal in accordance with a compared result, N-pieces of charge pumps, each of which generates a current in accordance with the up-signal and the down-signal inputted from each phase comparator, an adder for adding currents generated by the N-pieces of charge pumps, a loop filter for generating a control voltage in accordance with an added current by the adder, and a voltage control oscillator for generating the extracted clock signal of a frequency in accordance with control voltage. With this configuration, it is possible to prevent a retiming margin in a parallel digital interface from increasing.

Abstract: A clock recovery circuit, according to the present invention, generates a clock signal that continuously maintains a fixed phase to an input data signal. It is made up of a phase comparator, charge pumps, loop filter, VCO, frequency-divider, and selector. The VCO generates the frequency of a first clock signal in direct proportion to the value of a voltage signal given by the loop filter. The frequency-divider frequency-divides the first clock signal into a resulting second clock signal The selector selects either said first clock signal or said second clock signal to be a recovery clock, in conformity with a selective signal. This selective signal directs said selector to select said first clock signal when said input data signal is of a high frequency; otherwise, to select said second clock signal when said input data signal is of a low frequency. The charge pump outputs a VCO control electric current, with its amount being decided by said selective signal.

Abstract: In an oscillating circuit, an oscillator generates an oscillation signal with a frequency, increases the frequency of the oscillation signal in response to a frequency increase signal and decreases the frequency of the oscillation signal in response to a frequency decrease signal. A detecting unit receives the oscillation signal and a reference signal. The detecting unit outputs the frequency increase signal to the oscillator when a ratio of the frequency of the oscillation signal to a frequency of the reference signal is smaller than a first predetermined value, and outputs the frequency decrease signal to the oscillator when a ratio of the frequency of the oscillation signal to the frequency of the reference signal is larger than a second predetermined value.

Abstract: A high speed electrical level converting circuit which converts an input signal into an output signal having a different potential from that of the input signal. A falling edge detector detects the falling edge of the input signal when the input signal changes from a high potential to a low potential. A short circuiting device serves to drain charge accumulated at the output terminal for a predetermined duration in response to a signal from the falling edge detector so as to allow the level converting circuit to make a transition from a high output to a low output in a very fast manner.