Abstract: A logic simulator includes a storage device and a simulator part. The storage device stores a signal duration delay file which associates first signal duration information indicating duration of an input signal supplied to a logic gate of a logic circuit with first element delay value information indicating a first element delay value. The simulator part extracts first element delay value information associated with the first signal duration information corresponding to second signal duration information indicating duration of an input signal supplied to the logic gate when a logic simulation is performed by referring the signal duration delay file, and performs the logic simulation of the logic circuit based on the extracted first element delay value information. By setting element delay value taking duration of an input signal into account, highly accurate logic simulation can be achieved.