Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract: To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a semiconductor device in which an N channel type memory transistor, a selection core transistor, and a selection bulk transistor are respectively electrically coupled in series. The memory transistor and the selection core transistor are formed in a silicon layer of an SOI substrate, and the selection bulk transistor is formed in a semiconductor substrate. A word line is coupled to a memory gate electrode of the memory transistor, and a bit line is coupled to the selection bulk transistor. A write-in operation is performed while applying a counter voltage opposite in polarity to a voltage applied from the word line to the memory gate electrode to the bit line.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors.

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract: Multi-Project Wafers includes a plurality of chiplets from different IP owners. Non-relevant chiplets are implemented with IP protection to inhibit IP disclosure of non-relevant IP owners.

Abstract: A non-volatile semiconductor memory device is provided in which a variation of threshold voltages of non-written memory cells and a potential variation of a selected bit line in preventing generation of drain disturb phenomenon are minimized Source lines SL.sub.1 ', SL.sub.2 ', SL.sub.3 ' and SL.sub.4 ' are provided in parallel to word lines WL.sub.1, WL.sub.2, WL.sub.3 and WL.sub.4, respectively, and selectively. When a data is to be written in a memory cell C.sub.11, a potential of a selected word line WL.sub.1 is set to a high voltage V.sub.pp, potentials of non-selected word lines WL.sub.2, WL.sub.3 and WL.sub.4 are set to the drain disturb preventing voltage, for example, an intermediate voltage V.sub.pp /2 which is a half of the high voltage. Further, a potential of a selected bit line BL.sub.1 is set to a potential V.sub.dd which is lower than the high voltage V.sub.pp, non-selected bit lines BL.sub.2, BL.sub.3 and BL.sub.4 are made open. Further, a potential of a selected source line SL.sub.

Abstract: A non-volatile memory cell disclosed herein includes a pair of regions are provided in a channel region in contact respectively with source and drain to provide a symmetrical structure. A data erase is done by applying a high voltage to the source to produce avalanche breakdown between the source and the region to inject induced hot carriers into the floating gate and wherein the memory cell threshold voltage after erasure is converged to a constant value irrespective of the initial states, while the converged value may be controlled to a desired voltage by applying a suitable voltage to the control gate. Erasure sequence consisting in all bit erase and one verification is sufficient such that the erase sequence is simplified and erase time shortened.

Abstract: In order to cyclically implement isotropical and anisotropical etching of an interlayer insulator provided in a semiconductor wafer, two variable capacitors are provided for applying RF bias (power) to a triode type dry etching apparatus. The two variable capacitors are controlled such that cyclically, as one of the two capacitors exhibits maximum capacitance thereof, the other capacitor exhibits minimum capacitance thereof. As an alternative to the above, a wafer supporting table provided in a reactive chamber of an electron cyclotron resonance type apparatus, is cyclically supplied with a radio frequency (RF) bias and the ground potential. This cyclic application of the RF bias and the ground potential is controlled by a combination of a pulse generator and an amplitude modulation circuit both coupled to an RF signal generator. The via hole is effectively formed using the cyclic operations of the isotropic and anisotropic etching.

Abstract: In order to cyclically implement isotropical and anisotropical etching of an interlayer insulator provided in a semiconductor wafer, two variable capacitors are provided for applying RF bias (power) to a triode type dry etching apparatus. The two variable capacitors are controlled such that cyclically, as one of the two capacitors exhibits maximum capacitance thereof, the other capacitor exhibits minimum capacitance thereof. As an alternative to the above, a wafer supporting table provided in a reactive chamber of an electron cyclotron resonance type apparatus, is cyclically supplied with a radio frequency (RF) bias and the ground potential. This cyclic application of the RF bias and the ground potential is controlled by a combination of a pulse generator and an amplitude modulation circuit both coupled to an RF signal generator. The via hole is effectively formed using the cyclic operations of the isotropic and anisotropic etching.