Patents by Inventor Yasushige Tanaka

Yasushige Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RESERVOIR ASSEMBLY FOR PROVIDING CARDIOPLEGIC SOLUTION CONTAINING BICARBONATE ION, AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20220203009
    Abstract: The object of the invention is to provide a novel reservoir assembly for providing a cardioplegic solution and a method for manufacturing the same.
    Type: Application
    Filed: April 3, 2020
    Publication date: June 30, 2022
    Applicant: FUSO PHARMACEUTICAL INDUSTRIES, LTD.
    Inventors: Shogo TOKUOKA, Yasushige TANAKA, Shin-ichi INOUE, Tomoko MORI
  • Synchronous semiconductor device, and inspection system and method for the same
    Patent number: 6559669
    Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: May 6, 2003
    Assignee: Fujitsu Limited
    Inventors: Hiroyuki Sugamoto, Hidetoshi Tanaka, Yasushige Tanaka
  • Synchronous semiconductor device, and inspection system and method for the same
    Publication number: 20020066058
    Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.
    Type: Application
    Filed: March 30, 2001
    Publication date: May 30, 2002
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyuki Sugamoto, Hidetoshi Tanaka, Yasushige Tanaka