Abstract: The method of forming a highly reliabile multilayer interconnect in a semiconductor device is discussed. After forming a metal interconnect 2 on a substrate 1, a polyimide precursor is coated using a spinner 3. A fully integral polyimide film is then formed by treatment such as baking at a prescribed temperature.

Abstract: A method for making a ferroelectric thin film capacitor. A Ti adhesive layer is formed on a silicon substrate covered with a silicon oxide layer. On this, a Pt film is deposited as a lower capacitor electrode, over which a ferroelectric film of high permittivity, such a crystallized BST film, is deposited by sputtering. Then an upper Pt electrode is deposited over the BST film by sputtering to form a capacitor. Finally, the capacitor is heat-treated in an oxidizing atmosphere to eliminate any leakage holes, that cause leakage current, in the ferroelectric thin film caused by the sputtering.

Abstract: A method of making ferroelectric film capacitors with sufficient yield for application to ULSI. In a first embodiment, after formation of a first ferroelectric film as the capacitor ferroelectric film, a very thin second ferroelectric film is deposited to fill the cavity portions generated between the crystal grains. This reduces the leakage current and increases the capacitor yield. In second embodiment, the cavity portions are filled with an insulating layer.

Abstract: A method of making ferroelectric film capacitors with sufficient yield for application to ULSI. In a first embodiment, after formation of a first ferroelectric film as the capacitor ferroelectric film, a very thin second ferroelectric film is deposited to fill the cavity portions generated between the crystal grains. This reduces the leakage current and increases the capacitor yield. In second embodiment, the cavity portions are filled with an insulating layer.

Abstract: A semiconductor device with a multilayer wiring structure has an insulating substrate and first conductors formed on top of the insulating substrate with a groove between neighboring first conductors. An insulating film covers the first conductors as well as the grooves between the neighboring first conductors. A void serving to reduce electrostatic capacitance between the conductors is formed in the grooves. An interlayer insulating film is formed on top of the first conductors to prevent leakage current, and second conductors are formed on top of the interlayer insulating film.

Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).

Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to fore a top surface with rounded comers on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.

Abstract: A method for making ferroelectric thin film form capacitors that maintains the insulating characteristics of the thin film capacitors formed on the semiconductor devices while reducing the leakage current and ensuring a yield sufficient for applications to ULSIs such as DRAMs. A metal or oxide thereof, which contains structural elements of a metal forming the ferroelectric thin film, is formed as islands in the initial stage of formation or during the formation of a ferroelectric thin film in semiconductor devices. This suppresses the formation of columnar crystals.

Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g. TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.

Abstract: Generally, according to the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material. One embodiment of the present invention is a microelectronic structure comprising a supporting layer having a principal surface, and an adhesion layer overlying the principal surface of the supporting layer, wherein the adhesion layer comprises a top surface and an expanded, oxidized sidewall (e.g. TiO.sub.2 40).

Abstract: An improved method of forming a capacitor electrode for a microelectronic structure such as a dynamic read only memory is disclosed which has a high dielectric constant (HDC) material as a capacitor dielectric. According to an embodiment of the present invention, the sidewall of the adhesion layer (e.g. TiN 36) in a lower electrode is pre-oxidized after deposition of an unreactive noble metal layer (e.g. Pt 38) but before deposition of an HDC material (e.g. BST 42). An important aspect of the present invention is that the pre-oxidation of the sidewall generally causes a substantial amount of the potential sidewall expansion (and consequent noble metal layer deformation) to occur before deposition of the HDC material.

Abstract: Generally, the present invention utilizes a lower electrode comprising a sidewall spacer to form a top surface with rounded corners on which HDC material can be deposited without substantial cracking. An important aspect of the present invention is that the sidewall spacer does not reduce the electrical contact surface area between the lower electrode and the HDC material layer as compared to a similar structure containing a lower electrode without a sidewall spacer. One embodiment of the present invention is a microelectronic structure comprising a supporting layer (e.g. Si substrate 30) having a principal surface, a lower electrode overlying the principal surface of the supporting layer, and a high-dielectric-constant material layer (e.g. BST 44) overlying the top surface of the lower electrode. The lower electrode comprises an adhesion layer (e.g TiN 36), an unreactive layer (e.g. Pt 42), a sidewall spacer (e.g. SiO.sub.

Abstract: In one form of the invention, a method is disclosed for growing CaF.sub.2 on a silicon surface, comprising the steps of maintaining the silicon surface at a first temperature below approximately 500.degree. C., starting a deposition of CaF.sub.2 on the silicon surface, stopping the deposition, and then annealing the CaF.sub.2 in forming gas at a temperature below 600.degree. C.

Abstract: A semiconductor device having a large-capacitance capacitor in which an insulator film is formed underneath a film made of a material having a high dielectric constant, such as tantalum oxide, in such a manner that a portion of the insulator film underneath a defect region which is undesirably thin is thicker than other portions of the insulator film, thereby preventing occurrence of a failure in terms of dielectric strength and deterioration of the lifetime of the capacitor which would otherwise be caused by the existence of the defect region. Also disclosed is a process for producing such semiconductor device. Thus, it is possible to effectively prevent occurrence of problems which would otherwise be caused when a material having a high dielectric constant, such as tantalum oxide, is employed as a dielectric film of a capacitor, so that the reliability of a semiconductor having a large-capacitance capacitor is greatly improved.

Abstract: A semiconductor device having a large-capacitance capacitor in which an insulator film is formed underneath a film made of a material having a high dielectric constant, such as tantalum oxide, in such a manner that a portion of the insulator film underneath a defect region which is undesirably thin is thicker than other portions of the insulator film, thereby preventing occurrence of a failure in terms of dielectric strength and deterioration of the lifetime of the capacitor which would otherwise be caused by the existence of the defect region. Also disclosed is a process for producing such semiconductor device. Thus, it is possible to effectively prevent occurrence of problems which would otherwise be caused when a material having a high dielectric constant, such as tantalum oxide, is employed as a dielectric film of a capacitor, so that the reliability of a semiconductor having a large-capacitance capacitor is greatly improved.

Abstract: A reaction-preventing film is provided between a capacitor insulating film made of a material having a high dielectric constant, such as Ta.sub.2 O.sub.5, and an upper electrode in order to prevent a reaction of the upper electrode with the capacitor insulating film. This effectively prevents the reaction between the upper electrode and the capacitor caused by a heat treatment conducted after formation of the capacitor, and hence prevents an increase in leakage current caused by the reaction. Thus, the reliability of a semiconductor device is remarkably increased.

Abstract: A semiconductor memory device is provided such as the type having flip-flop memory cells each including two bipolar transistors in cross connection with each other. In certain embodiments, at least a part of a Schottky barrier diode or capacitor in the memory cell is formed under a digit line. This memory device is greatly reduced in its required area, and the Schottky barrier diode and capacitor are negligibly influenced by the digit line. In other embodiments, it is arranged to provide different electrodes for the Schottky barrier diode and the capacitor to optimize construction in a minimized space.

Abstract: A semiconductor device comprising a first electrode, a dielectric film and a second electrode which are stacked and formed on a semiconductor layer with the second electrode in contact with the semiconductor layer. A diode is formed of the second electrode and the semiconductor layer, and a capacitor is formed of the first electrode, the dielectric film and the second electrode.

Abstract: At least one layer of insulator film and single-crystal film are alternately stacked and deposited on a surface of a semiconductor substrate, and an impurity-doped region formed in each semiconductor film is used as a gate, source or drain of a MOS transistor.Thus, a three-dimensional semiconductor device is constructed in which MOS transistors are arranged, not only in the direction of the semiconductor substrate surface, but also in a direction perpendicular thereto.