Patents by Inventor Yasusuke Suzuki

Yasusuke Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8294236
    Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Mitsuhira, Takehiko Nakahara, Yasusuke Suzuki, Jun Sumino
  • Publication number: 20110057287
    Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
    Type: Application
    Filed: November 15, 2010
    Publication date: March 10, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Noriyuki MITSUHIRA, Takehiko NAKAHARA, Yasusuke SUZUKI, Jun SUMINO
  • Patent number: 7858490
    Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: December 28, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Noriyuki Mitsuhira, Takehiko Nakahara, Yasusuke Suzuki, Jun Sumino
  • Publication number: 20080213971
    Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
    Type: Application
    Filed: March 13, 2008
    Publication date: September 4, 2008
    Applicant: RENESAS TECHNOLOGY CORP
    Inventors: Noriyuki Mitsuhira, Takehiko Nakahara, Yasusuke Suzuki, Jun Sumino
  • Publication number: 20060035437
    Abstract: A semiconductor device having a memory cell area and a peripheral circuit area includes a silicon substrate and an isolation structure implemented by a silicon oxide film formed on a surface of the silicon substrate. A depth of the isolation structure in the memory cell area is smaller than a depth of the isolation structure in the peripheral circuit area, and an isolation height of the isolation structure in the memory cell area is substantially the same as an isolation height of the isolation structure in the peripheral circuit area. Reliability of the semiconductor device can thus be improved.
    Type: Application
    Filed: August 10, 2005
    Publication date: February 16, 2006
    Inventors: Noriyuki Mitsuhira, Takehiko Nakahara, Yasusuke Suzuki, Jun Sumino
  • Patent number: 5703582
    Abstract: A D/A converter of a current output type desirably compensates for changes in the switching characteristic that arise in each constant current circuit. The D/A converter generates an analog output current that is in response to the level of input digital data and outputs it from an output side by switching each of output currents of a plurality of constant current circuits either to the output side or to a non-output side, in response to the input digital data. The D/A converter performs feedback control, for values of the output currents for the constant current circuits, based on an analog output current at the non-output side during a period when the output currents of all of the constant current circuits are connected to the non-output sides.
    Type: Grant
    Filed: April 1, 1996
    Date of Patent: December 30, 1997
    Assignee: International Business Machines Corporation
    Inventors: Seiji Koyama, Tohru Nozawa, Asao Terukina, Yasusuke Suzuki