Patents by Inventor Yasutaka Arakawa

Yasutaka Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8283940
    Abstract: Provision of a probe device, a processing device and a probe test capable of performing an efficient wafer probe test. A probe device, comprising a plurality of measuring stages to which a plurality of probe cards for inspecting semiconductor wafers are connected, respectively; a first conveying portion for conveying a semiconductor wafer to a first measuring stage to which a first probe card is connected; a first inspection control portion for controlling the inspection of the semiconductor wafer by the first probe card; a receiving portion for receiving stage information including information showing nonuse of the first measuring stage from a processing device; a second conveying portion for conveying the semiconductor wafer to a second measuring stage, to which a second probe card different from the first probe card is connected, according to the received stage information; and a second inspection control portion for controlling the inspection of the semiconductor wafer by the second probe card.
    Type: Grant
    Filed: September 15, 2009
    Date of Patent: October 9, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasutaka Arakawa
  • Publication number: 20100148810
    Abstract: Provision of a probe device, a processing device and a probe test capable of performing an efficient wafer probe test. A probe device, comprising a plurality of measuring stages to which a plurality of probe cards for inspecting semiconductor wafers are connected, respectively; a first conveying portion for conveying a semiconductor wafer to a first measuring stage to which a first probe card is connected; a first inspection control portion for controlling the inspection of the semiconductor wafer by the first probe card; a receiving portion for receiving stage information including information showing nonuse of the first measuring stage from a processing device; a second conveying portion for conveying the semiconductor wafer to a second measuring stage, to which a second probe card different from the first probe card is connected, according to the received stage information; and a second inspection control portion for controlling the inspection of the semiconductor wafer by the second probe card.
    Type: Application
    Filed: September 15, 2009
    Publication date: June 17, 2010
    Inventor: Yasutaka ARAKAWA
  • Patent number: 7529631
    Abstract: A defect detection system includes a data acquiring section that acquires time series data of device parameter of each manufacturing device including an exposure device, and information on defect distribution in an area with a size smaller than a chip area size, a pattern classifying section that assembles the information on the defect distribution in units of shot or chip areas, and classifies the distributions to a defect pattern, a feature quantity calculating section that processes the time series data and calculates a feature quantity, a significant difference test section that calculates occurrence frequency distributions of the shot or chip area wherein the defect pattern to the feature quantity exists and does not exist, respectively, and determines the presence/absence of significant difference between the frequency distributions, and a defect detecting section that detects the device parameter corresponding to the feature quantity as the cause of defect of the defect pattern.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: May 5, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Matsushita, Yasutaka Arakawa, Junji Sugamoto
  • Publication number: 20080004823
    Abstract: A defect detection system includes a data acquiring section that acquires time series data of device parameter of each manufacturing device including an exposure device, and information on defect distribution in an area with a size smaller than a chip area size, a pattern classifying section that assembles the information on the defect distribution in units of shot or chip areas, and classifies the distributions to a defect pattern, a feature quantity calculating section that processes the time series data and calculates a feature quantity, a significant difference test section that calculates occurrence frequency distributions of the shot or chip area wherein the defect pattern to the feature quantity exists and does not exist, respectively, and determines the presence/absence of significant difference between the frequency distributions, and a defect detecting section that detects the device parameter corresponding to the feature quantity as the cause of defect of the defect pattern.
    Type: Application
    Filed: June 19, 2007
    Publication date: January 3, 2008
    Inventors: Hiroshi Matsushita, Yasutaka Arakawa, Junji Sugamoto