Patents by Inventor Yasutaka Iuchi

Yasutaka Iuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and method of forming the same
    Patent number: 11569185
    Abstract: A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.
    Type: Grant
    Filed: October 19, 2020
    Date of Patent: January 31, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Mitsunari Sukekawa, Shogo Omiya, Yasutaka Iuchi, Yoshinori Ikebuchi
  • CONDUCTIVE LAYERS IN MEMORY ARRAY REGION AND METHODS FOR FORMING THE SAME
    Publication number: 20230017813
    Abstract: Apparatuses and methods for manufacturing semiconductor memory devices are described. An example method includes: forming a conductive layer and sputtering the conductive layer with gas. The conductive layer includes a first portion having a top surface having a first height; and a second portion having a top surface having a second height lower than the first height. Sputtering the conductive layer with gas may be performed to remove the first portion of the conductive layer and increase the second height of the second portion of the conductive layer concurrently.
    Type: Application
    Filed: July 19, 2021
    Publication date: January 19, 2023
    Applicant: Micron Technology, Inc.
    Inventors: KENICHI SUGINO, MITSUNARI SUKEKAWA, YASUTAKA IUCHI, KEISUKE SHIMADA
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20220122930
    Abstract: A method for forming a multilayer conductive structure includes forming a first conductive portion; forming a second conductive portion containing ruthenium (Ru) therein on the first conductive portion; forming a third conductive portion on the second conductive portion; and performing a silicidation process on the second conductive portion.
    Type: Application
    Filed: October 19, 2020
    Publication date: April 21, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Mitsunari Sukekawa, Shogo Omiya, Yasutaka Iuchi, Yoshinori Ikebuchi
  • Conductive line construction, memory circuitry, and method of forming a conductive line construction
    Patent number: 11075274
    Abstract: A method of forming a conductive line construction comprises forming a structure comprising polysilicon-comprising material. Elemental titanium is directly against the polysilicon of the polysilicon-comprising material. Silicon nitride is directly against the elemental titanium. Elemental tungsten is directly against the silicon nitride. The structure is annealed to form a conductive line construction comprising the polysilicon-comprising material, titanium silicide directly against the polysilicon-comprising material, elemental tungsten, TiSixNy between the elemental tungsten and the titanium silicide, and one of (a) or (b), with (a) being the TiSixNy is directly against the titanium silicide, and (b) being titanium nitride is between the TiSixNy and the titanium silicide, with the TiSixNy being directly against the titanium nitride and the titanium nitride being directly against the titanium silicide. Structure independent of method is disclosed.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi, Akie Shimamura
  • Conductive Line Construction, Memory Circuitry, And Method Of Forming A Conductive Line Construction
    Publication number: 20200235219
    Abstract: A method of forming a conductive line construction comprises forming a structure comprising polysilicon-comprising material. Elemental titanium is directly against the polysilicon of the polysilicon-comprising material. Silicon nitride is directly against the elemental titanium. Elemental tungsten is directly against the silicon nitride. The structure is annealed to form a conductive line construction comprising the polysilicon-comprising material, titanium silicide directly against the polysilicon-comprising material, elemental tungsten, TiSixNy between the elemental tungsten and the titanium silicide, and one of (a) or (b), with (a) being the TiSixNy is directly against the titanium silicide, and (b) being titanium nitride is between the TiSixNy and the titanium silicide, with the TiSixNy being directly against the titanium nitride and the titanium nitride being directly against the titanium silicide. Structure independent of method is disclosed.
    Type: Application
    Filed: January 18, 2019
    Publication date: July 23, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi, Akie Shimamura
  • Method of forming semiconductor device including tungsten layer
    Patent number: 10438954
    Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi
  • Method of Forming Semiconductor Device Including Tungsten Layer
    Publication number: 20190035793
    Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.
    Type: Application
    Filed: September 18, 2018
    Publication date: January 31, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi
  • Method of forming semiconductor device including tungsten layer
    Patent number: 10109635
    Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: October 23, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi
  • Method of Forming Semiconductor Device Including Tungsten Layer
    Publication number: 20180083010
    Abstract: A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.
    Type: Application
    Filed: May 11, 2017
    Publication date: March 22, 2018
    Inventors: Kenichi Kusumoto, Yasutaka Iuchi