Abstract: A managing unit adds update information to an entry to be updated of a table updated prior to a change of a network configuration, and deletes the update information when the update of the table caused by the change of the network configuration is completed. A packet processing unit executes a plurality of pipeline processes using the table sequentially, and suspends executing the pipeline processes when the update information is added to any entry of the table. A reprocessing control unit stores an input packet in a reprocessing queue when the pipeline processes executed by the packet processing unit is suspended, and transfers the packet stored in the reprocessing queue to the input queue when update of the table to which the update information is added is all completed.

Abstract: A managing unit adds update information to an entry to be updated of a table updated prior to a change of a network configuration, and deletes the update information when the update of the table caused by the change of the network configuration is completed. A packet processing unit executes a plurality of pipeline processes using the table sequentially, and suspends executing the pipeline processes when the update information is added to any entry of the table. A reprocessing control unit stores an input packet in a reprocessing queue when the pipeline processes executed by the packet processing unit is suspended, and transfers the packet stored in the reprocessing queue to the input queue when update of the table to which the update information is added is all completed.

Abstract: A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.

Abstract: A PMOS output stage and an NMOS output stage of which output impedances are controlled in accordance with impedance codes, a gate control part which drives output transistors held by the PMOS output stage and the NMOS output stage, and a slew rate control part which generates bias voltages to control driving ability of the gate control part based on an input current are included, and manufacturing variability of an input current circuit generating an input current is corrected by using the impedance code by the slew rate control part.

Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Abstract: A level converter includes a level conversion circuit, which is provided between a reference power supply line having a reference voltage level and a first power supply line coupled to a first power supply outputting a first voltage level, which inputs a first signal and outputs a second signal, the first signal having a first logic level and a second logic level, the second signal having a first logic level and a second logic level; a control signal generating circuit to output a control signal having the reference voltage level when a second power supply outputting the second voltage level is turned off and the first voltage level when the second power supply is turned on; and a coupling circuit to control an electrically connection between the first power supply line and an output node of the level conversion circuit based on the control signal.

Abstract: Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is “0”, and outputs a signal input to a first input terminal when the set signal is “1”, and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is “0”, and outputs an output of the inverter when the set signal is “1” from the second output terminal.

Abstract: A semiconductor device includes a delay part configured to assign a delay to an input signal, a phase detector configured to detect a phase of an output signal output from the delay part, a setting part configured to set a stable operations range of the phase of the output signal based on phase information output from the phase detector, and an error detector configured to set an acceptable range corresponding to the stable operations range, determine whether a phase of the output signal falls within the acceptable range, and change the acceptable range based on an extraneous factor of an input signal of the delay part.

Abstract: Plural unit delay circuits connected in series and an output circuit that non-inverts or inverts and outputs an output signal in accordance with a set signal are included. A first unit delay circuit includes a selector that outputs a signal input to a second input terminal when the set signal is “0”, and outputs a signal input to a first input terminal when the set signal is “1”, and an inverter that inverts and outputs an output of the selector from a second output terminal. A second unit delay circuit includes an inverter that inverts the signal input to the first input terminal and outputs from a first output terminal, and a selector that outputs the signal input to the second input terminal when the set signal is “0”, and outputs an output of the inverter when the set signal is “1” from the second output terminal.

Abstract: A PMOS output stage and an NMOS output stage of which output impedances are controlled in accordance with impedance codes, a gate control part which drives output transistors held by the PMOS output stage and the NMOS output stage, and a slew rate control part which generates bias voltages to control driving ability of the gate control part based on an input current are included, and manufacturing variability of an input current circuit generating an input current is corrected by using the impedance code by the slew rate control part.

Abstract: In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Abstract: A semiconductor device including an input terminal to receive an input signal and an output terminal to output an output signal includes delay elements connected in series with the input terminal and each to assign the delay to the input signal input from the input terminal, selectors connected to output sides of the delay elements and each to select one of output signals of the delay elements based on a selection signal for selecting the one of the output signals of the delay elements to return the selected one of the output signals to the output terminal, and delay circuits disposed corresponding to the selectors and each to cause switching of the selection signal input into a corresponding one of the selectors to occur after switching of a signal level of the input signal input into the corresponding one of the selectors serving as a signal turning point.

Abstract: An A/D converter includes an adjusting circuit to adjust a total of an amount of change of ?? modulated data output from a ?? modulator and an amount of change of dummy data to be constant, and a level converting part supplied with the ?? modulated data. The level converting part includes a first level converter to output the ?? modulated data by converting a level of the ?? modulated data, and a second level converter to receive the dummy data from the adjusting circuit and interpolate dummy noise, in order to cancel a frequency dependence of noise with respect to the ?? modulated data.

Abstract: In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

Abstract: A clock generating apparatus includes a phase-difference measuring device for measuring a difference in phase between a reference clock and a feedback clock generated by a divider with a high-speed clock generated by a multiplier, an averager for averaging the measured phase difference, and an output clock generator for returning a self-generated output clock to the multiplier and the divider and generating an output clock synchronized with the reference clock by using the averaged phase difference and a generated operation clock. The multiplier generates the high-speed clock by multiplying the returned output clock, and the divider generates the feedback clock by dividing the returned output clock A frequency of generation of the output clock in the output clock generator is increased.

Abstract: An A/D converter includes an adjusting circuit to adjust a total of an amount of change of ?? modulated data output from a ?? modulator and an amount of change of dummy data to be constant, and a level converting part supplied with the ?? modulated data. The level converting part includes a first level converter to output the ?? modulated data by converting a level of the ?? modulated data, and a second level converter to receive the dummy data from the adjusting circuit and interpolate dummy noise, in order to cancel a frequency dependence of noise with respect to the ?? modulated data.

Abstract: The present invention provides an apparatus, method, and program for automatically generating setting information for a different model on the basis of settings previously made. Additionally, the present invention is directed to automatically determining one piece of setting information to be set for a different model on the basis of settings previously made. The present invention is also directed to automatically generating, on the basis of settings previously made, setting information that is to be set for a different model and that meets the user's intention.

Abstract: A digital signal processing apparatus includes a frame generator configured to generate a plurality of frames from a row of sample data of a time-domain, a part of each frame overlapping with adjoining frames, a Fourier transform unit configured to transform at least one of the generated frames into a frequency domain by Fourier transformation, an addition unit configured to add predetermined frequency characteristic to the transformed frame, and an inverse Fourier transform unit configured to transform the added frame into the time-domain by inverse Fourier transformation and to delete the overlap of the frame of the time-domain transformed.

Abstract: A clock generating apparatus includes a phase-difference measuring device for measuring a difference in phase between a reference clock and a feedback clock generated by a divider with a high-speed clock generated by a multiplier, an averager for averaging the measured phase difference, and an output clock generator for returning a self-generated output clock to the multiplier and the divider and generating an output clock synchronized with the reference clock by using the averaged phase difference and a generated operation clock. The multiplier generates the high-speed clock by multiplying the returned output clock, and the divider generates the feedback clock by dividing the returned output clock A frequency of generation of the output clock in the output clock generator is increased.

Abstract: The present invention provides an apparatus, method, and program for automatically generating setting information for a different model on the basis of settings previously made. Additionally, the present invention is directed to automatically determining one piece of setting information to be set for a different model on the basis of settings previously made. The present invention is also directed to automatically generating, on the basis of settings previously made, setting information that is to be set for a different model and that meets the user's intention.