Abstract: A source driver 130 includes a first latch 131 outputting a first data signal D1(1) having multiple bits (e.g., eight bits), a second latch 132 outputting a second data signal D2(1) by latching the first data signal D1(1) in a plurality of steps in units of one or more bits, a DAC 133 converting the second data signal D2(1) into an analog signal A(1), and an amplifier 134 receiving the analog signal A(1) to output a source signal S(1). The second latch 132 latches the first data signal D1(1), e.g., one bit at every clock, one bit at every plurality of clocks, a plurality of bits at every clock, or a plurality of bits at every plurality of clocks.

Abstract: A source driver 130 includes a first latch 131 outputting a first data signal D1(1) having multiple bits (e.g., eight bits), a second latch 132 outputting a second data signal D2(1) by latching the first data signal D1(1) in a plurality of steps in units of one or more bits, a DAC 133 converting the second data signal D2(1) into an analog signal A(1), and an amplifier 134 receiving the analog signal A(1) to output a source signal S(1). The second latch 132 latches the first data signal D1(1), e.g., one bit at every clock, one bit at every plurality of clocks, a plurality of bits at every clock, or a plurality of bits at every plurality of clocks.