Patents by Inventor Yasutaka Nakahsiba

Yasutaka Nakahsiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8604617
    Abstract: A semiconductor device with a transistor region has a first conductor pattern formed within a multilayer interconnect structure positioned under a signal line and above the transistor region. The first conductor pattern is coupled to ground or a power supply and overlaps the transistor region. The signal line overlaps the first conductor pattern.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: December 10, 2013
    Assignee: Renesas Electronic Corporation
    Inventors: Masayuki Furumiya, Yasutaka Nakahsiba, Akira Tanabe