Patents by Inventor Yasutaka Nishioka
Yasutaka Nishioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200405162Abstract: A cuff unit of the present invention includes a first wall and a second wall that face each other with an object which has a rod shape interposed therebetween, an actuator that is capable of moving the first wall and the second wall in parallel with each other in a direction in which the first wall and the second wall relatively approach each other or separate from each other, a pressing fluid bag that is provided on a surface of the first wall on a side facing the object and that receives supply of a fluid from outside to inflate and press the object, and a restraining fluid bag that is provided on a surface of the second wall on a side facing the object and that receives supply of a fluid from outside to inflate along the periphery of the object.Type: ApplicationFiled: September 16, 2020Publication date: December 31, 2020Applicants: OMRON HEALTHCARE CO., LTD., THE UNIVERSITY OF SHIGA PREFECTURE, OMRON CORPORATIONInventors: Yasutaka NISHIOKA, Kenta AZUMA, Minoru TANIGUCHI, Chisato TAWARA, Tsuyoshi HAMAGUCHI
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Patent number: 10874306Abstract: A soft gripper that surrounds and grips an outer peripheral surface of an object, the soft gripper includes an elongated first actuator and an elongated second actuator, which are deformed in response to supply of a fluid. The first actuator and the second actuator extend from bases of the first and second actuators toward opposite sides each other. When receiving the supply of the fluid, each of the first and second actuators sequentially surrounds the object from the base toward a side of a leading end of the each of the first and second actuators.Type: GrantFiled: May 25, 2018Date of Patent: December 29, 2020Assignees: OMRON HEALTHCARE CO., LTD., UNIVERSITY OF SHIGA PREFECTURE, OMRON CORPORATIONInventors: Yasutaka Nishioka, Wataru Masuda, Masao Shimizu, Tsuyoshi Hamaguchi, Minoru Taniguchi
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Patent number: 10157955Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: January 19, 2017Date of Patent: December 18, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20180271386Abstract: A soft gripper that surrounds and grips an outer peripheral surface of an object, the soft gripper includes an elongated first actuator and an elongated second actuator, which are deformed in response to supply of a fluid. The first actuator and the second actuator extend from bases of the first and second actuators toward opposite sides each other. When receiving the supply of the fluid, each of the first and second actuators sequentially surrounds the object from the base toward a side of a leading end of the each of the first and second actuators.Type: ApplicationFiled: May 25, 2018Publication date: September 27, 2018Applicants: OMRON HEALTHCARE CO., LTD., THE UNIVERSITY OF SHIGA PREFECTURE, OMRON CORPORATIONInventors: Yasutaka NISHIOKA, Wataru MASUDA, Masao SHIMIZU, Tsuyoshi HAMAGUCHI, Minoru TANIGUCHI
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Publication number: 20170133430Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: January 19, 2017Publication date: May 11, 2017Inventors: Akie YUTANI, Yasutaka NISHIOKA
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Patent number: 9583532Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: February 8, 2016Date of Patent: February 28, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20160155772Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: February 8, 2016Publication date: June 2, 2016Inventors: Akie YUTANI, Yasutaka NISHIOKA
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Patent number: 9281329Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: May 15, 2015Date of Patent: March 8, 2016Assignee: RENESAS ELETRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20150249103Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: May 15, 2015Publication date: September 3, 2015Inventors: Akie YUTANI, Yasutaka NISHIOKA
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Patent number: 9064771Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating fAh and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: April 21, 2014Date of Patent: June 23, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20140225174Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: April 21, 2014Publication date: August 14, 2014Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Akie YUTANI, Yasutaka Nishioka
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Patent number: 8728853Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: GrantFiled: April 24, 2009Date of Patent: May 20, 2014Assignee: Renesas Electronics CorporationInventors: Akie Yutani, Yasutaka Nishioka
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Publication number: 20120037968Abstract: By selectively anisotropically etching a stack film formed to cover a plurality of photodiodes and a gate electrode layer of a MOS transistor, the stack film remains on each of the plurality of photodiodes to form a lower antireflection coating and the stack film remains on a sidewall of the gate electrode layer to form a sidewall. Using the gate electrode layer and the sidewall as a mask, an impurity is introduced to form a source/drain region of the MOS transistor. After the impurity was introduced, an upper antireflection coating is formed at least on a lower antireflection coating. At least any of the upper antireflection coating and the lower antireflection coating is etched such that the antireflection coatings on the two respective photodiodes are different in thickness from each other.Type: ApplicationFiled: April 24, 2009Publication date: February 16, 2012Inventors: Akie Yutani, Yasutaka Nishioka
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Patent number: 8008730Abstract: To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.Type: GrantFiled: July 13, 2009Date of Patent: August 30, 2011Assignee: Renesas Electronics CorporationInventors: Shoichi Fukui, Noboru Morimoto, Yasutaka Nishioka, Junko Izumitani, Atsushi Ishii
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Publication number: 20100052062Abstract: To provide a manufacturing method of a semiconductor device which can improve the reliability of the semiconductor device. A first insulating film for covering a semiconductor element formed in a semiconductor substrate is formed by a thermal CVD method or the like which has a good embedding property. A second insulating film is formed to cover the first insulating film by a plasma CVD method which has excellent humidity resistance. A plug is formed to penetrate the first insulating film and the second insulating film. A third insulating film comprised of a low-k film having a relatively low dielectric constant is formed over the second insulating film. A wiring is formed in the third insulating film by a damascene technique to be electrically coupled to the plug.Type: ApplicationFiled: July 13, 2009Publication date: March 4, 2010Inventors: Shoichi Fukui, Noboru Morimoto, Yasutaka Nishioka, Junko Izumitani, Atsushi Ishii
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Patent number: 7605085Abstract: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.Type: GrantFiled: September 18, 2006Date of Patent: October 20, 2009Assignees: Renesas Technology Corp., Panasonic CorporationInventors: Kazuo Tomita, Keiji Hashimoto, Yasutaka Nishioka, Susumu Matsumoto, Mitsuru Sekiguchi, Akihisa Iwasaki
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Publication number: 20070007658Abstract: First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.Type: ApplicationFiled: September 18, 2006Publication date: January 11, 2007Applicants: RENESAS TECHNOLOGY CORP., MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kazuo TOMITA, Keiji HASHIMOTO, Yasutaka NISHIOKA, Susumu MATSUMOTO, Mitsuru SEKIGUCHI, Akihisa IWASAKI
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Publication number: 20060163730Abstract: A first nitrogen-containing insulating film is formed under a low dielectric constant film, in which a via hole is formed, with a first nitrogen-non-containing insulating film interposed between the first nitrogen-containing insulating film and the low dielectric constant film. A second nitrogen-containing insulating film is formed over the low dielectric constant film with a second nitrogen-non-containing insulating film interposed therebetween.Type: ApplicationFiled: April 7, 2004Publication date: July 27, 2006Inventors: Susumu Matsumoto, Mitsuru Sekiguchi, Yasutaka Nishioka, Kazuo Tomita, Akihisa Iwasaki, Keiji Hashimoto
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Patent number: 6898851Abstract: It is an object to provide a semiconductor device having a buried multilayer wiring structure in which generation of a resolution defect of a resist pattern is suppressed and generation of a defective wiring caused by the resolution defect is reduced. After a via hole (7) reaching an etching stopper film (4) is formed, annealing is carried out at 300 to 400° C. with the via hole (7) opened. As an annealing method, it is possible to use both a method using a hot plate and a method using a heat treating furnace. In order to suppress an influence on a lower wiring (20) which has been manufactured, heating is carried out for a short time of approximately 5 to 10 minutes by using the hot plate.Type: GrantFiled: November 21, 2003Date of Patent: May 31, 2005Assignees: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.Inventors: Yasutaka Nishioka, Junjiro Sakai, Shingo Tomohisa, Susumu Matsumoto, Fumio Iwamoto, Michinari Yamanaka
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Publication number: 20050035457Abstract: First wirings and first dummy wirings are in a p-SiOC film on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film 22. Dummy vias are formed on the periphery of isolated vias.Type: ApplicationFiled: March 4, 2004Publication date: February 17, 2005Applicants: Renesas Technology Corp., Matsushita Electric Industrial Co., Ltd.Inventors: Kazuo Tomita, Keiji Hashimoto, Yasutaka Nishioka, Susumu Matsumoto, Mitsuru Sekiguchi, Akihisa Iwasaki