Patents by Inventor Yasutaka Ohno

Yasutaka Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packet insertion interval control system and packet insertion interval control method
    Patent number: 6771600
    Abstract: A packet insertion interval control system includes a counting unit (32), having a first bit field for managing an insertion interval of a management packet required to be cyclically inserted and a second bit field for specifying a logic path for forwarding the management packet, for executing such a counting operation as to periodically cycle the first bit field and the second bit field, and a control unit (31) for executing control for specifying, when a count value indicated by the first bit field of the counting unit is a predetermined value, the logic path for forwarding the management packet on the basis of a count value indicated by the second bit field of the counting unit, and for inserting the management packet into the specified logic path. With this architecture, it is feasible to restrain an increase in quantity of the hardware and flexibly correspond to changes in the number of connections (number of channels) and the cell insertion interval (packet insertion interval) per communication system.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: August 3, 2004
    Assignee: Fujitsu Limited
    Inventors: Kenichi Kawarai, Takeshi Terada, Yasutaka Ohno, Yasuhiro Ooba
  • Packet insertion interval control system and packet insertion interval control method
    Publication number: 20010015957
    Abstract: A packet insertion interval control system includes a counting unit (32), having a first bit field for managing an insertion interval of a management packet required to be cyclically inserted and a second bit field for specifying a logic path for forwarding the management packet, for executing such a counting operation as to periodically cycle the first bit field and the second bit field, and a control unit (31) for executing control for specifying, when a count value indicated by the first bit field of the counting unit is a predetermined value, the logic path for forwarding the management packet on the basis of a count value indicated by the second bit field of the counting unit, and for inserting the management packet into the specified logic path. With this architecture, it is feasible to restrain an increase in quantity of the hardware and flexibly correspond to changes in the number of connections (number of channels) and the cell insertion interval (packet insertion interval) per communication system.
    Type: Application
    Filed: January 12, 2001
    Publication date: August 23, 2001
    Applicant: Fujitsu Limited
    Inventors: Kenichi Kawarai, Takeshi Terada, Yasutaka Ohno, Yasuhiro Ooba