Patents by Inventor Yasutaka Sugimoto

Yasutaka Sugimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088847
    Abstract: An amplification circuit includes an amplification transistor connected to a signal input terminal, a power supply circuit configured to supply a bias voltage to the amplification transistor, a resistor disposed in series to a bias path connecting the power supply circuit and the amplification transistor, a transistor that is connected to the bias path and the power supply circuit and that is a simulated transistor for the amplification transistor, and a detection diode connected to the signal input terminal and the bias path between the resistor and a gate of the amplification transistor.
    Type: Application
    Filed: August 29, 2023
    Publication date: March 14, 2024
    Inventors: Yasutaka SUGIMOTO, Koji NASU
  • Patent number: 11924968
    Abstract: The laminate of the present disclosure is a laminate including multiple glass ceramic layers each containing quartz and a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal. An Al2O3 content of a surface layer portion of the laminate is higher than an Al2O3 content of an inner layer portion of the laminate, and a M2O content of the surface layer portion is lower than a M2O content of the inner layer portion.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: March 5, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yutaka Senshu, Yasutaka Sugimoto, Sadaaki Sakamoto
  • Patent number: 11903126
    Abstract: The laminate of the present disclosure includes multiple glass ceramic layers each containing quartz and a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal. The B concentration of a surface layer portion of the laminate is lower than the B concentration of an inner layer portion of the laminate.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: February 13, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Sadaaki Sakamoto, Yutaka Senshu, Yasutaka Sugimoto
  • Patent number: 11760686
    Abstract: The glass ceramic material of the present disclosure contains a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal, and a filler that contains quartz, Al2O3, and ZrO2. The glass ceramic material contains the glass in an amount of 57.4% by weight or more and 67.4% by weight or less, the quartz in the filler in an amount of 29% by weight or more and 39% by weight or less, the Al2O3 in the filler in an amount of 1.8% by weight or more and 5% by weight or less, and the ZrO2 in the filler in an amount of 0.3% by weight or more and 1.8% by weight or less.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: September 19, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasutaka Sugimoto, Sadaaki Sakamoto, Yutaka Senshu
  • Publication number: 20230117436
    Abstract: A glass ceramic that contains a glass containing Si, B, Al, and Zn and aggregates. The glass has a SiO2 content of 20% by weight to 55% by weight, a B2O3 content of 15% by weight to 30% by weight, Al2O3, and ZnO, wherein a weight ratio of the SiO2 to the B2O3 (SiO2/B2O3) is 1.21 or higher, and a weight ratio of the Al2O3 to the ZnO (Al2O3/ZnO) is 0.8 to 1.3. A TiO2 content, a ZrO2 content, a SnO2 content, and a Sr0 content in the glass each are 0% by weight to 5% by weight. The aggregates include 20% by weight to 50% by weight of SiO2, 1% by weight to 10% by weight of TiO2, 3% by weight or less of ZrO2, and 1% by weight or less of ZnO each relative to the weight of the glass ceramic.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 20, 2023
    Inventors: Yasutaka SUGIMOTO, Taichi WATANABE
  • Publication number: 20230109726
    Abstract: A glass that contains Si, B, Al, and Zn. The glass has SiO2 at a content of 15% by weight to 65% by weight, B2O3 at a content of 11% by weight to 30% by weight, Al2O3, and ZnO, wherein a weight ratio of the SiO2 to the B2O3 (SiO2/B2O3) is 1.21 or higher, and a weight ratio of the Al2O3 to the ZnO (Al2O3/ZnO) is 0.75 to 1.64, and wherein an alkaline-earth metal is excluded as a material contained in the glass.
    Type: Application
    Filed: December 14, 2022
    Publication date: April 13, 2023
    Inventors: Taichi WATANABE, Yasutaka SUGIMOTO, Jun URAKAWA
  • Publication number: 20230030235
    Abstract: An amplifier unit includes an amplifier, a bias circuit, an inductor, a variable resistor circuit, and a control circuit. The amplifier includes an amplifier transistor that amplifies an input radio-frequency signal. The bias circuit is connected to the amplifier. The inductor is connected between and in series with the amplifier and the bias circuit. The variable resistor circuit is connected to the inductor. The control circuit includes a measuring circuit and a comparison circuit. The measuring circuit measures an amplification characteristic value of the amplifier transistor. The comparison circuit compares the amplification characteristic value measured by the measuring circuit with a reference value. The control circuit controls the variable resistor circuit based on a comparison result of the comparison circuit.
    Type: Application
    Filed: October 7, 2022
    Publication date: February 2, 2023
    Inventor: Yasutaka SUGIMOTO
  • Publication number: 20220216478
    Abstract: An active material includes, as constituent elements, silicon, oxygen, a first element, a second element, and a third element. The first element includes boron, phosphorus, or both. The second element includes at least one of an alkali metal element, a transition element, or a typical element. The typical element excludes silicon, oxygen, boron, phosphorus, an alkali metal element, and an alkaline earth metal element. The third element includes an alkaline earth metal element. The content of silicon with respect to all the constituent elements excluding oxygen and carbon is 60 at % or greater and 98 at % or less. The content of the first element with respect to all the constituent elements excluding oxygen and carbon is 1 at % or greater and 25 at % or less. The content of the second element with respect to all the constituent elements excluding oxygen and carbon is 1 at % or greater and 34 at % or less.
    Type: Application
    Filed: March 25, 2022
    Publication date: July 7, 2022
    Inventors: Daisuke ITO, Yuji KINTAKA, Yasutaka SUGIMOTO
  • Publication number: 20220006427
    Abstract: An amplifier circuit includes an input terminal to which a radio frequency signal is input, an amplifier transistor that has a control terminal and amplifies the radio frequency signal, a bias circuit that includes an emitter-follower circuit or a source-follower circuit and supplies a bias current to the control terminal of the amplifier transistor, an inductor arranged in series between an emitter of the emitter-follower circuit and the control terminal of the amplifier transistor or between a source of the source-follower circuit and the control terminal of the amplifier transistor, and a variable resistance circuit connected to the inductor.
    Type: Application
    Filed: September 22, 2021
    Publication date: January 6, 2022
    Inventor: Yasutaka SUGIMOTO
  • Publication number: 20210315100
    Abstract: The laminate of the present disclosure is a laminate including multiple glass ceramic layers each containing quartz and a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal. An Al2O3 content of a surface layer portion of the laminate is higher than an Al2O3 content of an inner layer portion of the laminate, and a M2O content of the surface layer portion is lower than a M2O content of the inner layer portion.
    Type: Application
    Filed: June 18, 2021
    Publication date: October 7, 2021
    Inventors: Yutaka SENSHU, Yasutaka SUGIMOTO, Sadaaki SAKAMOTO
  • Publication number: 20210309562
    Abstract: The glass ceramic material of the present disclosure contains a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal, and a filler that contains quartz, Al2O3, and ZrO2. The glass ceramic material contains the glass in an amount of 57.4% by weight or more and 67.4% by weight or less, the quartz in the filler in an amount of 29% by weight or more and 39% by weight or less, the Al2O3 in the filler in an amount of 1.8% by weight or more and 5% by weight or less, and the ZrO2 in the filler in an amount of 0.3% by weight or more and 1.8% by weight or less.
    Type: Application
    Filed: June 11, 2021
    Publication date: October 7, 2021
    Inventors: Yasutaka SUGIMOTO, Sadaaki SAKAMOTO, Yutaka SENSHU
  • Publication number: 20210310878
    Abstract: A temperature detection circuit (1) includes a first transistor (Q1) of a bipolar type, and a second transistor (Q2) of a bipolar type, wherein the first transistor (Q1) and the second transistor (Q2) form a current mirror circuit (10), and the temperature of the amplifier circuit (30) is detected based on a temperature change of the first transistor (Q1) and the second transistor (Q2).
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Nobukazu SUZUKI, Hideyo YAMASHIRO, Yasutaka SUGIMOTO, Takayuki KAWANO
  • Publication number: 20210307162
    Abstract: The laminate of the present disclosure includes multiple glass ceramic layers each containing quartz and a glass that contains SiO2, B2O3, Al2O3, and M2O, where M is an alkali metal. The B concentration of a surface layer portion of the laminate is lower than the B concentration of an inner layer portion of the laminate.
    Type: Application
    Filed: June 11, 2021
    Publication date: September 30, 2021
    Inventors: Sadaaki SAKAMOTO, Yutaka SENSHU, Yasutaka SUGIMOTO
  • Patent number: 11114355
    Abstract: A power module includes a power wiring line provided with a power element, a glass ceramic multilayer substrate provided with a control element to control the power element, and a highly heat-conductive ceramic substrate made of a ceramic material having higher thermal conductivity than a glass ceramic contained in the glass ceramic multilayer substrate. The power wiring line is disposed on the highly heat-conductive ceramic substrate, and the glass ceramic multilayer substrate is disposed directly on the highly heat-conductive ceramic substrate.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Hayakawa, Yasutaka Sugimoto, Tomoki Kato, Yoichi Moriya
  • Patent number: 11107741
    Abstract: A composite ceramic multilayer substrate includes a glass ceramic insulating layer including a wiring layer and a highly thermally conductive ceramic insulating layer made of a ceramic material having a higher thermal conductivity than the glass ceramic insulating layer. The glass ceramic insulating layer is provided on at least one main surface of the highly thermally conductive ceramic insulating layer directly and/or with a wiring layer interposed therebetween. When viewed in a direction perpendicular or substantially perpendicular to a main surface of the composite ceramic multilayer substrate, the composite ceramic multilayer substrate includes at least one heat generating element-mounting portion surrounded by the glass ceramic insulating layer and at which a heat generating element-mounting wiring line provide on the main surface of the highly thermally conductive ceramic insulating layer is exposed.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 31, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tomoki Kato, Yasutaka Sugimoto, Yoichi Moriya, Takahiro Hayakawa
  • Publication number: 20210184344
    Abstract: An antenna module (100) includes a dielectric substrate (160) having a multilayer structure, a first radiation electrode (122), a second radiation electrode (121), and a ground electrode (GND). The second radiation electrode (121) is arranged between the first radiation electrode (122) and the ground electrode (GND) in a lamination direction of the dielectric substrate (160). In the dielectric substrate (160), a hollow portion (150) is disposed in at least a portion between the first radiation electrode (122) and the second radiation electrode (121).
    Type: Application
    Filed: March 2, 2021
    Publication date: June 17, 2021
    Inventors: Tomoshige FURUHI, Saneaki ARIUMI, Hisao HAYAFUJI, Tomoki KATO, Yasutaka SUGIMOTO
  • Patent number: 10931236
    Abstract: Provided is a detector circuit that includes: a first transistor that has an alternating current signal input to a base thereof, and that outputs a first detection signal that depends on the alternating current signal from a collector thereof; a second transistor that has the first detection signal input to a base thereof, and that outputs a second detection signal that depends on the first detection signal from a collector thereof; and an alternating current signal path along which the alternating current signal is supplied to the base of the second transistor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 23, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasutaka Sugimoto, Hiroyuki Hirooka
  • Patent number: 10906839
    Abstract: A mixed powder for a low temperature cofired ceramic material that contains 65 to 80 parts by weight of SiO2, 5 to 25 parts by weight of BaO, 1 to 10 parts by weight of Al2O3, 0.1 to 5 parts by weight of MnO, 0.1 to 5 parts by weight of B2O3, and 0.1 to less than 3 parts by weight of Li2O. The ceramic sintered body is used for, for example, ceramic electronic components, e.g., a multilayer circuit board or a coupler.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: February 2, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasutaka Sugimoto, Kazuhiro Kaneko
  • Publication number: 20200244224
    Abstract: Provided is a detector circuit that includes: a first transistor that has an alternating current signal input to a base thereof, and that outputs a first detection signal that depends on the alternating current signal from a collector thereof; a second transistor that has the first detection signal input to a base thereof, and that outputs a second detection signal that depends on the first detection signal from a collector thereof; and an alternating current signal path along which the alternating current signal is supplied to the base of the second transistor.
    Type: Application
    Filed: April 14, 2020
    Publication date: July 30, 2020
    Inventors: Yasutaka SUGIMOTO, Hiroyuki HIROOKA
  • Patent number: 10666199
    Abstract: Provided is a detector circuit that includes: a first transistor that has an alternating current signal input to a base thereof, and that outputs a first detection signal that depends on the alternating current signal from a collector thereof; a second transistor that has the first detection signal input to a base thereof, and that outputs a second detection signal that depends on the first detection signal from a collector thereof; and an alternating current signal path along which the alternating current signal is supplied to the base of the second transistor.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: May 26, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yasutaka Sugimoto, Hiroyuki Hirooka