Abstract: Disclosed is an AC characteristics measurement system that includes a flip-flop arranged in a loop of a ring oscillator; a clock generating circuit that receives a signal propagated in said loop of said ring oscillator and generates a clock signal to be supplied to said flip-flop; a delay adjustment circuit that receives a signal propagated in said loop of said ring oscillator and generates a data signal to be supplied to said flip-flop and that receives a control signal and variably controls the time difference between a transition edge of said data signal to be supplied to said flip-flop and an effective edge of said clock signal to be supplied to said flip-flop, based on said control signal; and a setup-hold changeover circuit that is provided at a preceding stage of said flip-flop and that switches the temporal before and after relation between a transition edge of said data signal supplied to said flip-flop and an effective edge of said clock signal, responsive to a control signal for performing changeov

Abstract: Disclosed is an output buffer circuit provided with a pre-emphasis function, including a first buffer circuit, receiving a first logic signal to drive a transmission line, and a second buffer circuit. The second buffer circuit includes an inverting buffer, receiving a second logic signal that is in a predetermined logical relationship with respect to the aforementioned first logic signal, and having outputs connected in common with an output of the aforementioned first buffer circuit, a first switch, connected across the inverting buffer and a first power supply, and controlled to be turned on or off based on a signal supplied to a control terminal, and a second switch, connected across the inverting buffer and a second power supply and controlled to be turned on or off based on a signal supplied to a control terminal in association operatively with the first switch.

Abstract: Disclosed is an AC characteristics measurement system that includes a flip-flop arranged in a loop of a ring oscillator; a clock generating circuit that receives a signal propagated in said loop of said ring oscillator and generates a clock signal to be supplied to said flip-flop; a delay adjustment circuit that receives a signal propagated in said loop of said ring oscillator and generates a data signal to be supplied to said flip-flop and that receives a control signal and variably controls the time difference between a transition edge of said data signal to be supplied to said flip-flop and an effective edge of said clock signal to be supplied to said flip-flop, based on said control signal; and a setup-hold changeover circuit that is provided at a preceding stage of said flip-flop and that switches the temporal before and after relation between a transition edge of said data signal supplied to said flip-flop and an effective edge of said clock signal, responsive to a control signal for performing changeov

Abstract: Disclosed is an output buffer circuit provided with a pre-emphasis function, including a first buffer circuit, receiving a first logic signal to drive a transmission line, and a second buffer circuit. The second buffer circuit includes an inverting buffer, receiving a second logic signal that is in a predetermined logical relationship with respect to the aforementioned first logic signal, and having outputs connected in common with an output of the aforementioned first buffer circuit, a first switch, connected across the inverting buffer and a first power supply, and controlled to be turned on or off based on a signal supplied to a control terminal, and a second switch, connected across the inverting buffer and a second power supply and controlled to be turned on or off based on a signal supplied to a control terminal in association operatively with the first switch.

Abstract: Disclosed is a complementary signal generation circuit that can suppress the distortion of an eye pattern due to a change in signal delay caused by jitter or a change in the rise and fall of a signal caused by a manufacturing factor. An inverter 11 inverts an input signal 101 and generates a first internal signal 104, and an inverter 12 inverts the first internal signal 104 and generates a second internal signal 105. When the first internal signal 104 goes high, a flip-flop 1 reduces the level of an in-phase signal 103 to low, and increases the level of an antiphase signal 102 to high. Thus, when the fall of the in-phase signal is delayed, the flip-flop also delays the rise of the antiphase signal and suppresses the distortion of the eye pattern. And when the ON resistances of transistors Qn1 and Qn2 are changed due to a manufacturing factor, RC series circuits 2 and 3 suppress the change in the driving capability.

Abstract: Disclosed is a complementary signal generation circuit that can suppress the distortion of an eye pattern due to a change in signal delay caused by jitter or a change in the rise and fall of a signal caused by a manufacturing factor. An inverter 11 inverts an input signal 101 and generates a first internal signal 104, and an inverter 12 inverts the first internal signal 104 and generates a second internal signal 105. When the first internal signal 104 goes high, a flip-flop 1 reduces the level of an in-phase signal 103 to low, and increases the level of an antiphase signal 102 to high. Thus, when the fall of the in-phase signal is delayed, the flip-flop also delays the rise of the antiphase signal and suppresses the distortion of the eye pattern. And when the ON resistances of transistors Qn1 and Qn2 are changed due to a manufacturing factor, RC series circuits 2 and 3 suppress the change in the driving capability.

Abstract: An output buffer circuit 1 comprises an output transistor section 10, a first and a second driving means 40, 50, and a first and a second switch circuits 60, 70. The output transistor section 10 comprises PMOS 11, 13, and NMOS 12, 14. Each source terminal of the PMOS 11, 13 is connected to VDD, each source terminal of the NMOS 12, 14 is connected to GND, and each drain terminal of the PMOS 11, 13 and NMOS 12, 14 are all connected to an output terminal N1 of the output buffer circuit 1. The driving capability of the PMOS 13 is set to be larger than that of PMOS 11, and the driving capability of the NMOS 14 is set to be larger than that of NMOS 12.

Abstract: An output buffer circuit 1 comprises an output transistor section 10, a first and a second driving means 40, 50, and a first and a second switch circuits 60, 70. The output transistor section 10 comprises PMOS 11, 13, and NMOS 12, 14. Each source terminal of the PMOS 11, 13 is connected to VDD, each source terminal of the NMOS 12, 14 is connected to GND, and each drain terminal of the PMOS 11, 13 and NMOS 12, 14 is all connected to an output terminal N1 of the output buffer circuit 1. The driving capability of the PMOS 13 is set to be larger than that of PMOS 11, and the driving capability of the NMOS 14 is set to be larger than that of NMOS 12.

Abstract: An electrostatic protection circuit protects an internal circuit from electric charge which is applied via an electrode pad. The above electrostatic protection circuit mainly includes a protection transistor portion, a second transistor and a third transistor. In this case, the protection transistor portion includes a first transistor having a first gate electrode in order to protect the internal circuit by discharging the electric charge. The second transistor controls so as to keep the first gate electrode into a floating state before the power source is introduced. The third transistor gives a predetermined potential into the first gate electrode.