Abstract: A transmission-line loss equalizing circuit includes an equalizer, a gain control circuit for controlling the gain of the equalizer based upon the peak value of an equalized output, a slicer for slicing the equalized output and outputting a data pulse, a timing extraction pulse and an equalization control pulse, a DC feedback level detector for detecting a DC component of the equalized output and feeding the DC component back to the equalizer, and an attenuating circuit provided as an initial stage of the equalizer. A plurality of .sqroot.fAGC circuits constructing the equalizer are cascade-connected and constructed by a differential non-inverting amplifier.

Abstract: An alarm termination apparatus includes: a bi-directionally accessible random access memory for storing alarm bits sampled from a plurality of parallel inputs at memory locations; a flip-flop circuit for temporarily storing a first alarm bit read from one of the memory locations of the memory and for outputting the first alarm bit to an output transmission line; and a selector for receiving a second alarm bit sampled from the parallel inputs and for receiving the stored first alarm bit from the flip-flop circuit, the selector selectively outputting the second alarm bit or the first alarm bit to the above one of the memory locations of the memory in accordance with a value of a select pulse, wherein the temporary storing of the first alarm bit from the memory into the flip-flop circuit and the selective outputting of the first alarm bit or the second alarm bit to the memory by the selector are controlled to sequentially take place.