Patents by Inventor Yasutake Yaguchi

Yasutake Yaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110291253
    Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.
    Type: Application
    Filed: August 5, 2011
    Publication date: December 1, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiyuki FUKUDA, Yoshihiro TOMITA, Hisashi UMEDA, Yasutake YAGUCHI
  • Patent number: 7993980
    Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.
    Type: Grant
    Filed: September 15, 2008
    Date of Patent: August 9, 2011
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Fukuda, Yoshihiro Tomita, Hisashi Umeda, Yasutake Yaguchi
  • Publication number: 20110080928
    Abstract: To provide a laser device having high strength against mechanical stress. The laser device includes: a laser element; a plate-like lead frame including through-holes, and on whose front plane the laser element is mounted; lead terminals; trenches provided between an end of the lead frame in a laser emission direction of the laser element and the through-holes; and a resin dam formed on the front plane of the lead frame using a molding resin to protrude in an area surrounding the laser element including positions of the through-holes, and having an open part in the laser emission direction. The molding resin further fills the through-holes and the trenches, and bonds the lead frame and the resin dam by sealing together a part of each of the lead terminals and a part of the front plane and the back plane of the lead frame, in a vicinity of the lead terminals.
    Type: Application
    Filed: September 22, 2010
    Publication date: April 7, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Noriyuki YOSHIKAWA, Yasutake YAGUCHI
  • Patent number: 7521288
    Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: April 21, 2009
    Assignee: Panasonic Corporation
    Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
  • Publication number: 20090091013
    Abstract: A lead frame of the present invention includes: a die pad on which a device is mounted; a first connection terminal which is provided around the die pad, and the lower surface of which serves as an external terminal; a second connection terminal which is provided around the die pad and electrically independent of the die pad, and the upper surface of which serves as an external terminal; a bent part provided between the first and the second connection terminals and connecting the first and the second connection terminals; and an outer frame. The bent part is bending-processed in a direction perpendicular to a face of the die pad. Within the outer frame, electronic component regions are formed adjoining each other and each including a die pad, and the first and the second connection terminals. The adjoining electronic components are connected through the first or the second connection terminal.
    Type: Application
    Filed: September 15, 2008
    Publication date: April 9, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toshiyuki Fukuda, Yoshihiro Tomita, Hisashi Umeda, Yasutake Yaguchi
  • Publication number: 20070187811
    Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.
    Type: Application
    Filed: March 14, 2007
    Publication date: August 16, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
  • Patent number: 7239021
    Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: July 3, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
  • Patent number: 7138706
    Abstract: A semiconductor device with excellent heat dissipation characteristics that can achieve a high reliability when mounted in electronic equipment such as a cellular phone or the like and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of semiconductor chips mounted on the substrate by stacking one on top of another, and an encapsulation resin layer made of encapsulation resin. Among the plurality of semiconductor chips, a first semiconductor chip as an uppermost semiconductor chip is mounted with a surface thereof on which a circuit is formed facing toward the substrate, and the encapsulation resin layer is formed so that at least a surface of the first semiconductor chip opposite to the surface on which the circuit is formed and a part of side surfaces of the first semiconductor chip are exposed to the outside of the encapsulation resin layer.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: November 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Kouichi Yamauchi, Yasutake Yaguchi
  • Publication number: 20060091563
    Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.
    Type: Application
    Filed: November 21, 2005
    Publication date: May 4, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Yasutake Yaguchi
  • Patent number: 6992396
    Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: January 31, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Yasutake Yaguchi
  • Patent number: 6954001
    Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: October 11, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
  • Publication number: 20050012214
    Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.
    Type: Application
    Filed: August 17, 2004
    Publication date: January 20, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
  • Publication number: 20050003580
    Abstract: A stacked chip semiconductor device including: a substrate having electrode pads; a first semiconductor chip that is flip-chip-packaged on the substrate via a first adhesive layer; a second semiconductor chip that is mounted on an upper part of the first semiconductor chip and that has electrode pads; wires for electrically connecting the electrode pads of the second semiconductor chip and the electrode pads of the substrate; and a molded resin for encapsulating the first semiconductor chip, the second semiconductor chip and the wires, the first adhesive layer forming a fillet at the periphery of the first semiconductor chip. The first semiconductor chip is disposed with its central axis being offset from a central axis of the substrate, the offset being provided so that the first semiconductor chip is shifted toward a side opposite to a side where the fillet has a maximum length from the periphery of the first semiconductor chip.
    Type: Application
    Filed: June 30, 2004
    Publication date: January 6, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Arai, Takashi Yui, Fumito Itou, Yasutake Yaguchi, Toshitaka Akahoshi
  • Patent number: 6784557
    Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: August 31, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi
  • Publication number: 20040126926
    Abstract: A semiconductor device has a substrate having electrode pads, a first semiconductor chip mounted on the substrate with a first adhesion layer interposed therebetween, a second semiconductor chip mounted on the first semiconductor chip with a second adhesion layer interposed therebetween and having electrode pads on the upper surface thereof, wires for bonding the electrode pads of the substrate and the electrode pads of the second semiconductor chip to each other, and a mold resin sealing therein the first and second semiconductor chips and the wires. The peripheral edge portion of the first adhesion layer is protruding outwardly from the first semiconductor chip and the peripheral edge portion of the second semiconductor chip is protruding outwardly beyond the peripheral edge portion of the first semiconductor chip.
    Type: Application
    Filed: August 28, 2003
    Publication date: July 1, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Yasutake Yaguchi
  • Publication number: 20040051168
    Abstract: A semiconductor device with excellent heat dissipation characteristics that can achieve a high reliability when mounted in electronic equipment such as a cellular phone or the like and a method for manufacturing the same are provided. The semiconductor device includes a substrate, a plurality of semiconductor chips mounted on the substrate by stacking one on top of another, and an encapsulation resin layer made of encapsulation resin. Among the plurality of semiconductor chips, a first semiconductor chip as an uppermost semiconductor chip is mounted with a surface thereof on which a circuit is formed facing toward the substrate, and the encapsulation resin layer is formed so that at least a surface of the first semiconductor chip opposite to the surface on which the circuit is formed and a part of side surfaces of the first semiconductor chip are exposed to the outside of the encapsulation resin layer.
    Type: Application
    Filed: June 24, 2003
    Publication date: March 18, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshiyuki Arai, Takashi Yui, Yoshiaki Takeoka, Fumito Itou, Kouichi Yamauchi, Yasutake Yaguchi
  • Publication number: 20030116867
    Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.
    Type: Application
    Filed: December 2, 2002
    Publication date: June 26, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshifumi Nakamura, Ryuichi Sahara, Nozomi Shimoishizaka, Kazuyuki Kainou, Keiji Miki, Kazumi Watase, Yasutake Yaguchi