Patents by Inventor Yasutomo Maehara
Yasutomo Maehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8754333Abstract: A printed circuit board includes a cell portion which includes cells having a plurality of through bores are arranged in a base material; and a base material portion which exists around an outer edge of the cell portion. The base material is formed of a prepreg, the prepreg includes a fiber material in which fiber threads are oriented in a first direction and in a second direction which is perpendicular to the first direction, and a resin material in which the fiber material is impregnated. The through bores are arranged along a third direction between the first direction and the second direction, wherein one side of the outer edges of the cell extends along the third direction.Type: GrantFiled: October 7, 2011Date of Patent: June 17, 2014Assignee: Fujitsu LimitedInventors: Hideaki Yoshimura, Kenji Iida, Yasutomo Maehara
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Patent number: 8186052Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.Type: GrantFiled: July 15, 2008Date of Patent: May 29, 2012Assignee: Fujitsu LimitedInventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Publication number: 20120097442Abstract: A printed circuit board includes a cell portion which includes cells having a plurality of through bores are arranged in a base material; and a base material portion which exists around an outer edge of the cell portion. The base material is formed of a prepreg, the prepreg includes a fiber material in which fiber threads are oriented in a first direction and in a second direction which is perpendicular to the first direction, and a resin material in which the fiber material is impregnated. The through bores are arranged along a third direction between the first direction and the second direction, wherein one side of the outer edges of the cell extends along the third direction.Type: ApplicationFiled: October 7, 2011Publication date: April 26, 2012Applicant: Fujitsu LimitedInventors: Hideaki YOSHIMURA, Kenji Iida, Yasutomo Maehara
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Patent number: 8153908Abstract: The circuit board is capable of tightly bonding a cable layer on a base member even if thermal expansion coefficients of the base member and the cable layer are significantly different. The circuit board comprises: the base member; and the cable layer being laminated on the base member with anchor patterns, which are electrically conductive layers formed on a surface of the base member.Type: GrantFiled: July 15, 2008Date of Patent: April 10, 2012Assignee: Fujitsu LimitedInventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Patent number: 8151456Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.Type: GrantFiled: July 18, 2008Date of Patent: April 10, 2012Assignee: Fujitsu LimitedInventors: Yasutomo Maehara, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Patent number: 8119923Abstract: A circuit board has a low thermal expansion coefficient that suits the thermal expansion coefficient of an element to be mounted thereupon and can prevent the occurrence of delamination and cracking of a core layer when the circuit board is used in a low temperature environment. The circuit board is constructed by laminating a core layer and at least one wiring layer, where the at least one wiring layer has slightly smaller external dimensions in a planar direction than the core layer.Type: GrantFiled: August 8, 2008Date of Patent: February 21, 2012Assignee: Fujitsu LimitedInventors: Hideaki Yoshimura, Kenji Fukuzono, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Takashi Nakagawa, Shin Hirano, Takashi Kanda
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Patent number: 8119925Abstract: The core layer of a core substrate is made of carbon fibers impregnated with resin. When the temperature of the core layer increases, the core layer suffers from an increase in the thickness because of thermal expansion of the resin. The core layer is sandwiched between the insulating layers containing glass fibers. The insulating layers serve to suppress an increase in the thickness of the core layer resulting from the thermal expansion of the core layer. Thermal stress is suppressed in the core substrate.Type: GrantFiled: February 20, 2009Date of Patent: February 21, 2012Assignee: Fujitsu LimitedInventors: Hideaki Yoshimura, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Takashi Nakagawa, Shin Hirano
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Patent number: 8110749Abstract: Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder along the inward wall surface of the small-sized through hole. The filling material and the core layer are uniformly distributed within the specific area in the in-plane direction of the core substrate. This results in suppression of uneven distribution of thermal stress in the core layer in the in-plane direction of the core layer.Type: GrantFiled: February 20, 2009Date of Patent: February 7, 2012Assignee: Fujitsu LimitedInventors: Hideaki Yoshimura, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano
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Publication number: 20120024586Abstract: A printed wiring board including a substrate that includes wiring through-hole portions where wiring through-holes which each penetrate the substrate from a surface on a front side of the substrate to a surface on a back side of the substrate, the wiring through-hole portions being made using a dielectric material having a thermal expansion coefficient different from a thermal expansion coefficient of the substrate; and thermal-expansion adjusting portions produced by filling prepared-holes with the dielectric material, the prepared-holes being produced at a surface of the substrate. The surface is partitioned into predetermined blocks, in each of which the thermal-expansion adjusting portions are placed in a layout that minimizes a difference between a thermal expansion coefficient in the block in a length direction and a thermal expansion coefficient in the block in a width direction according to a placement of the wiring through-hole portions in the block.Type: ApplicationFiled: April 29, 2011Publication date: February 2, 2012Applicant: FUJITSU LIMITEDInventors: Hideaki YOSHIMURA, Kenji IIDA, Yasutomo MAEHARA
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Patent number: 8035037Abstract: The core substrate is capable of securely preventing short circuit between an electrically conductive core section and a plated through-hole section. The core substrate comprises: an electrically conductive core section having a pilot hole, through which a plated through-hole section is formed; electrically conductive layers coating the inner face of the pilot hole and a surface of the core section; a gas purging hole being formed in the conductive layer coating the surface of the core section; an insulating material filling a space between the inner face of the pilot hole and an outer circumferential face of the plated through-hole section; and cable layers being laminated on both side faces of the core section.Type: GrantFiled: July 10, 2008Date of Patent: October 11, 2011Assignee: Fujitsu LimitedInventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Patent number: 7943001Abstract: A process for producing a multilayer board includes the steps of applying a bonding ink to the terminal of the first substrate, the bonding ink including a thermosetting resin containing a filler and a curing agent, the filler being formed of metal particles plated with solder, the metal particles each having a first melting point, and the solder having a second melting point lower than the first melting point; bonding the second substrate to a bonding sheet composed of a thermosetting resin and having a through hole disposed in a portion corresponding to the terminal of the second substrate; and heating and pressurizing the first and second substrates with the bonding sheet in such a manner that the terminals are opposite each other to effect curing of the bonding sheet and the bonding ink and to form an integral structure.Type: GrantFiled: January 4, 2007Date of Patent: May 17, 2011Assignee: Fujitsu LimitedInventors: Takashi Nakagawa, Seiichi Sugano, Kenji Iida, Yasutomo Maehara, Hitoshi Suzuki, Kaoru Sugimoto, Kenji Fukuzono, Takashi Kanda, Hiroaki Date, Tomohisa Yagi
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Publication number: 20090294161Abstract: The core layer of a core substrate is made of carbon fibers impregnated with resin. When the temperature of the core layer increases, the core layer suffers from an increase in the thickness because of thermal expansion of the resin. The core layer is sandwiched between the insulating layers containing glass fibers. The insulating layers serve to suppress an increase in the thickness of the core layer resulting from the thermal expansion of the core layer. Thermal stress is suppressed in the core substrate.Type: ApplicationFiled: February 20, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventors: Hideaki YOSHIMURA, Kenji IIDA, Tomoyuki ABE, Yasutomo MAEHARA, Takashi NAKAGAWA, Shin HIRANO
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Publication number: 20090294166Abstract: Large-sized through holes are formed in a core layer of a printed wiring board. Large-sized vias are formed in the shape of a cylinder along the inward wall surfaces of the large-sized through holes located within a specific area. A filling material fills the inner space of the large-sized via. A small-sized through hole penetrates through the corresponding filling material along the longitudinal axis of the small-sized through hole. A small-sized via is formed in the shape of a cylinder along the inward wall surface of the small-sized through hole. The filling material and the core layer are uniformly distributed within the specific area in the in-plane direction of the core substrate. This results in suppression of uneven distribution of thermal stress in the core layer in the in-plane direction of the core layer.Type: ApplicationFiled: February 20, 2009Publication date: December 3, 2009Applicant: FUJITSU LIMITEDInventors: Hideaki YOSHIMURA, Kenji IIDA, Tomoyuki ABE, Yasutomo MAEHARA, Shin HIRANO
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Publication number: 20090094825Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; plating the base member so as to coat an inner face of the through-hole with a plated layer; applying photo resist on the base member; optically exposing and developing the photo resist so as to form a resist pattern, which coats at least a planar area of the through-hole; and etching an electrically conductive layer formed on the surface of the base member. The resist pattern is formed so as to separate an area of exposing the conductive layer a prescribed distance away from an edge of the through-hole, and the prescribed length is longer than a distance of etching a side face of the conductive layer in the etching step.Type: ApplicationFiled: July 18, 2008Publication date: April 16, 2009Applicant: FUJITSU LIMITEDInventors: Yasutomo MAEHARA, Kenji Iida, Tomoyuki Abe, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Publication number: 20090095509Abstract: In the core substrate, short circuit between an electrically conductive core section and a plated through-hole section can be securely prevented and cables can be formed in a high dense state. The core substrate comprises: the electrically conductive core section having a pilot hole, through which the plated through-hole section is formed; cable layers being respectively laminated on the both side faces of the core section; a plated layer coating an inner face of the pilot hole; and an insulating material filling a space between the plated layer and an outer circumferential face of the plated through-hole section.Type: ApplicationFiled: August 8, 2008Publication date: April 16, 2009Applicant: FUJITSU LIMITEDInventors: Shin Hirano, Kenji Iida, Yasutomo Maehara, Tomoyuki Abe, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Publication number: 20090094824Abstract: The method of producing a substrate comprises the steps of: forming a through-hole in a base member; filling the through-hole with an insulating material; performing electroless plating to coat the surface of the base member, in which the through-hole has been filled with the insulating material, with an electroless-plated layer; applying photo resist on the electroless-plated layer formed on the surface of the base member; optically exposing and developing the photo resist so as to form a resist pattern coating an end face of the through-hole filled with the insulating material; etching an electrically conductive layer formed on the surface of the base member with using the resist pattern as a mask; and removing the resist pattern coating the end face of the through-hole from the base member with using the electroless-plated layer as a release layer.Type: ApplicationFiled: July 15, 2008Publication date: April 16, 2009Applicant: FUJITSU LIMITEDInventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Publication number: 20090095511Abstract: The circuit board is capable of tightly bonding a cable layer on a base member even if thermal expansion coefficients of the base member and the cable layer are significantly different. The circuit board comprises: the base member; and the cable layer being laminated on the base member with anchor patterns, which are electrically conductive layers formed on a surface of the base member.Type: ApplicationFiled: July 15, 2008Publication date: April 16, 2009Applicant: FUJITSU LIMITEDInventors: Kenji IIDA, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Publication number: 20090098391Abstract: The core member constitutes a core substrate of a circuit board. The core member comprises: a carbon fiber-reinforced core section, in which prepregs including carbon fibers are thermocompression-bonded; and copper foils being respectively thermocompression-bonded on the both side faces of the carbon fiber-reinforced core section with prepregs including glass fibers. The pregregs including glass fibers are composed of resin, whose melting temperature range is higher than that of resin composing the pregregs including carbon fibers.Type: ApplicationFiled: August 8, 2008Publication date: April 16, 2009Applicant: FUJITSU LIMITEDInventors: Takashi NAKAGAWA, Kenji IIDA, Yasutomo MAEHARA, Shin HIRANO, Tomoyuki ABE, Hideaki YOSHIMURA, Seigo YAMAWAKI, Norikazu OZAKI
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Publication number: 20090095524Abstract: The core substrate is capable of securely preventing short circuit between an electrically conductive core section and a plated through-hole section. The core substrate comprises: an electrically conductive core section having a pilot hole, through which a plated through-hole section is formed; electrically conductive layers coating the inner face of the pilot hole and a surface of the core section; a gas purging hole being formed in the conductive layer coating the surface of the core section; an insulating material filling a space between the inner face of the pilot hole and an outer circumferential face of the plated through-hole section; and cable layers being laminated on both side faces of the core section.Type: ApplicationFiled: July 10, 2008Publication date: April 16, 2009Applicant: FUJITSU LIMITEDInventors: Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Shin Hirano, Takashi Nakagawa, Hideaki Yoshimura, Seigo Yamawaki, Norikazu Ozaki
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Publication number: 20090084590Abstract: A circuit board has a low thermal expansion coefficient that suits the thermal expansion coefficient of an element to be mounted thereupon and can prevent the occurrence of delamination and cracking of a core layer when the circuit board is used in a low temperature environment. The circuit board is constructed by laminating a core layer and at least one wiring layer, where the at least one wiring layer has slightly smaller external dimensions in a planar direction than the core layer.Type: ApplicationFiled: August 8, 2008Publication date: April 2, 2009Applicant: FUJITSU LIMITEDInventors: Hideaki YOSHIMURA, Kenji Fukuzono, Kenji Iida, Tomoyuki Abe, Yasutomo Maehara, Takashi Nakagawa, Shin Hirano, Takashi Kanda