Patents by Inventor Yasutomo Matsuba

Yasutomo Matsuba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12225219
    Abstract: Systems and techniques are described herein for processing video data. For instance, a process can include obtaining first encoded data for a first portion of an image, the image encoded in a plurality of independently decodable portions. The process can further include generating first intermediate data for the first portion of the image, storing the first intermediate data in a bitstream order, obtaining second encoded data for a second portion of the image, generating second intermediate data for the second portion of the image, storing the second intermediate data in the bitstream order, wherein the first intermediate data is stored separate from the second intermediate data, processing the first intermediate data and the second intermediate data in a raster scan order across the first portion of the image and the second portion of the image to generate a part of the image.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: February 11, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Tomoyuki Naito, Yasutomo Matsuba
  • Patent number: 12132928
    Abstract: Systems and techniques are provided for processing video data. For example, an apparatus may obtain one or more first sets of collocated motion vector data and one or more second sets of collocated motion vector data, associated with a respective first and second block of video data included in a current frame of video data. The apparatus may project the one or more first sets of collocated motion vector data into a first projected motion field associated with a first buffer and project the one or more second sets of collocated motion vector data into the first projected motion field associated with the first buffer. Based on projecting the one or more first sets and one or more second sets of collocated motion vector data, the apparatus may decode the first block of video data based on the first projected motion field associated with the first buffer.
    Type: Grant
    Filed: September 2, 2022
    Date of Patent: October 29, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Gopi Madhan Dabbadi, Yasutomo Matsuba, Sandeep Nellikatte Srivatsa, Ashish Mishra
  • Publication number: 20240298016
    Abstract: A device includes a decoder that includes a spatial prediction engine, a temporal prediction engine, a reconstruction engine, and a decoded picture buffer. The device also includes a controller configured to cause the decoder to, in a base resolution mode, reconstruct a base resolution version of a block of a frame using the reconstruction engine and at least one of the spatial prediction engine or the temporal prediction engine. The controller is also configured to cause the decoder to, in an enhanced resolution mode, generate an enhanced resolution version of the block using the reconstruction engine and the at least one of the spatial prediction engine or the temporal prediction engine.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 5, 2024
    Inventors: Hua-I CHANG, Khalid TAHBOUB, Yasutomo MATSUBA, Kai WANG
  • Publication number: 20240236333
    Abstract: Systems and techniques are described herein for processing video data. For instance, a process can include determining a number of rows of pixels for one or more portions of an image. The process can further include obtaining first encoded data for a first portion of the image, decoding the first encoded data to generate first pixel data for the number of rows of pixels of the first portion of the image, outputting the first pixel data for the first portion of the image to a memory, and outputting an indication that the first portion of the image is available.
    Type: Application
    Filed: January 5, 2023
    Publication date: July 11, 2024
    Inventors: Tomoyuki NAITO, Yasutomo MATSUBA
  • Publication number: 20240205434
    Abstract: Systems and techniques are described herein for processing video data. For instance, a process can include obtaining first encoded data for a first portion of an image, the image encoded in a plurality of independently decodable portions. The process can further include generating first intermediate data for the first portion of the image, storing the first intermediate data in a bitstream order, obtaining second encoded data for a second portion of the image, generating second intermediate data for the second portion of the image, storing the second intermediate data in the bitstream order, wherein the first intermediate data is stored separate from the second intermediate data, processing the first intermediate data and the second intermediate data in a raster scan order across the first portion of the image and the second portion of the image to generate a part of the image.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 20, 2024
    Inventors: Tomoyuki NAITO, Yasutomo MATSUBA
  • Patent number: 12010325
    Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: June 11, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Kapil Garg, Gaurav Avinash Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
  • Publication number: 20240114174
    Abstract: A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.
    Type: Application
    Filed: December 15, 2023
    Publication date: April 4, 2024
    Inventors: Vivienne Sze, Madhukar Budagavi, Akira Osamoto, Yasutomo Matsuba
  • Publication number: 20240080474
    Abstract: Systems and techniques are provided for processing video data. For example, an apparatus may obtain one or more first sets of collocated motion vector data and one or more second sets of collocated motion vector data, associated with a respective first and second block of video data included in a current frame of video data. The apparatus may project the one or more first sets of collocated motion vector data into a first projected motion field associated with a first buffer and project the one or more second sets of collocated motion vector data into the first projected motion field associated with the first buffer. Based on projecting the one or more first sets and one or more second sets of collocated motion vector data, the apparatus may decode the first block of video data based on the first projected motion field associated with the first buffer.
    Type: Application
    Filed: September 2, 2022
    Publication date: March 7, 2024
    Inventors: Gopi Madhan DABBADI, Yasutomo MATSUBA, Sandeep Nellikatte SRIVATSA, Ashish MISHRA
  • Patent number: 11849148
    Abstract: A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Vivienne Sze, Madhukar Budagavi, Akira Osamoto, Yasutomo Matsuba
  • Patent number: 11638020
    Abstract: A device includes a first bitstream engine and a second bitstream engine. The first bitstream engine is configured to decode a first portion of a first video frame of a plurality of video frames to generate first decoded portion data. The first bitstream engine is also configured to generate synchronization information based on completion of decoding the first portion. The second bitstream engine is configured to, based on the synchronization information, initiate decoding of a second portion of a particular video frame to generate second decoded portion data. The second bitstream engine uses the first decoded portion data during decoding of the second portion of the particular video frame. The particular video frame includes the first video frame or a second video frame of the plurality of video frames.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 25, 2023
    Assignee: Qualcomm Incorporated
    Inventors: Yasutomo Matsuba, Kai Wang
  • Publication number: 20230059060
    Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.
    Type: Application
    Filed: October 20, 2022
    Publication date: February 23, 2023
    Inventors: Kapil Garg, Gaurav Avinash Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
  • Patent number: 11516477
    Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: November 29, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Kapil Garg, Gaurav Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
  • Publication number: 20220321899
    Abstract: A device includes a first bitstream engine and a second bitstream engine. The first bitstream engine is configured to decode a first portion of a first video frame of a plurality of video frames to generate first decoded portion data. The first bitstream engine is also configured to generate synchronization information based on completion of decoding the first portion. The second bitstream engine is configured to, based on the synchronization information, initiate decoding of a second portion of a particular video frame to generate second decoded portion data. The second bitstream engine uses the first decoded portion data during decoding of the second portion of the particular video frame. The particular video frame includes the first video frame or a second video frame of the plurality of video frames.
    Type: Application
    Filed: March 30, 2021
    Publication date: October 6, 2022
    Inventors: Yasutomo MATSUBA, Kai WANG
  • Patent number: 11463716
    Abstract: An example apparatus includes a first line buffer and a second line buffer, where each memory location in the first line buffer and the second line buffer corresponds to a row or column of a palette token block. The first line buffer may store two of the neighboring palette token values (e.g., above and left palette token values), and the second line buffer may store one of the neighboring palette token value (e.g., above-left). As a video coder is coding palette token values, the video coder may shift values stored in the first line buffer to the overwrite a memory location in the second line buffer, and overwrite values stored in the first line buffer based in part on the row or column of the palette token block to which the memory locations in the first and second line buffer correspond.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: October 4, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Yasutomo Matsuba, David Chu
  • Publication number: 20220272367
    Abstract: An example apparatus includes a first line buffer and a second line buffer, where each memory location in the first line buffer and the second line buffer corresponds to a row or column of a palette token block. The first line buffer may store two of the neighboring palette token values (e.g., above and left palette token values), and the second line buffer may store one of the neighboring palette token value (e.g., above-left). As a video coder is coding palette token values, the video coder may shift values stored in the first line buffer to the overwrite a memory location in the second line buffer, and overwrite values stored in the first line buffer based in part on the row or column of the palette token block to which the memory locations in the first and second line buffer correspond.
    Type: Application
    Filed: February 25, 2021
    Publication date: August 25, 2022
    Inventors: Yasutomo Matsuba, David Chu
  • Publication number: 20220256167
    Abstract: An example apparatus includes a first frame buffer configured to store video data; a second frame buffer configured to store video data; and one or more processors configured to: reconstruct samples of a first block of a current picture of video data; store, in parallel, a compressed version of the samples of the first block of video data in the first frame buffer and an uncompressed version of the samples of the first block of video data in the second frame buffer; and responsive to determining to reconstruct a second block of the current picture of video data using intra block copy: obtain, from the second frame buffer, samples of a predictor block located in the current picture of video data, the predictor block at least partially overlapping the first block of video data; and predict, based on the obtained samples of the predictor block, samples of the second block.
    Type: Application
    Filed: February 11, 2021
    Publication date: August 11, 2022
    Inventors: Kapil Garg, Gaurav Patil, Yasutomo Matsuba, Vladan Andrijanic, Prasanth Gomatam, Rajesh Chowdary Chitturi
  • Publication number: 20210314627
    Abstract: A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Vivienne Sze, Madhukar Budagavi, Akira Osamoto, Yasutomo Matsuba
  • Patent number: 11070844
    Abstract: A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 20, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vivienne Sze, Madhukar Budagavi, Akira Osamoto, Yasutomo Matsuba
  • Publication number: 20190303174
    Abstract: Systems and methods implemented in firmware and hardware domains may include writing by the firmware domain configuration information to a memory for a plurality of passes of hardware processing, programming by the hardware domain configuration registers with the configuration information retrieved from the memory, and processing by the hardware domain the plurality of passes in accordance with the configuration information programmed in the configuration registers. The configuration registers may be programmed after the configuration information are written to the memory.
    Type: Application
    Filed: March 28, 2019
    Publication date: October 3, 2019
    Inventors: Srikanth ALAPARTHI, Harikrishna REDDY, Yasutomo MATSUBA, Ashish MEDEWAR, Siddharth KHIMSARA
  • Publication number: 20190166384
    Abstract: A method and a video processor for preventing start code confusion. The method includes aligning bytes of a slice header relating to slice data when the slice header is not byte aligned or inserting differential data at the end of the slice header before the slice data when the slice header is byte aligned, performing emulation prevention byte insertion on the slice header, and combine the slice header and the slice data after performing emulation prevention byte insertion.
    Type: Application
    Filed: January 31, 2019
    Publication date: May 30, 2019
    Inventors: Vivienne Sze, Madhukar Budagavi, Akira Osamoto, Yasutomo Matsuba