Abstract: According to one embodiment, a designing apparatus includes a register position determining module, a net list generator, and a layout data generator. The register position determining module determines a register position on a layout of a semiconductor integrated circuit from a hardware description. The net list generator generates a net list according to the register position. The layout data generator generates layout data based on the net list. The layout data indicates the layout of the semiconductor integrated circuit.

Abstract: According to one embodiment, a designing apparatus includes a register position determining module, a net list generator, and a layout data generator. The register position determining module determines a register position on a layout of a semiconductor integrated circuit from a hardware description. The net list generator generates a net list according to the register position. The layout data generator generates layout data based on the net list. The layout data indicates the layout of the semiconductor integrated circuit.

Abstract: A semiconductor integrated circuit includes a random access memory; a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes a failure test; a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on condition that the memory test pattern is read without being rewritten; and a combinational logic circuit that can configure a system logic circuit along with the scan chain. The random access memory outputs a data signal read from the memory test pattern, by a read command signal that is attributable to the logic test pattern and is passed the combinational logic circuit. The test result that is attributed to the read data signal and is passed through the combinational logic circuit is input to the scan chain. The scan chain shifts out the test result.

Abstract: A semiconductor integrated circuit includes a random access memory; a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes a failure test; a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on condition that the memory test pattern is read without being rewritten; and a combinational logic circuit that can configure a system logic circuit along with the scan chain. The random access memory outputs a data signal read from the memory test pattern, by a read command signal that is attributable to the logic test pattern and is passed the combinational logic circuit. The test result that is attributed to the read data signal and is passed through the combinational logic circuit is input to the scan chain. The scan chain shifts out the test result.