Patents by Inventor Yasutoshi AKIBA

Yasutoshi AKIBA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220392380
    Abstract: A circuit device includes a storing section configured to store a rendering image and a warp processing section. The warp processing section includes a coordinate converting section, a coordinate-address converting section, and an output section. The coordinate converting section converts, with coordinate conversion based on warp parameters and rotation correction parameters, an output coordinate, which is a coordinate on a display image, into an input coordinate, which is a coordinate on the rendering image. The coordinate-address converting section converts the input coordinate into a read address of the storing section. The output section reads out pixel data of the rendering image from the read address of the storing section and outputs, based on the read-out pixel data, pixel data in the output coordinate of the display image.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 8, 2022
    Inventors: Yasutoshi AKIBA, Jeffrey ERIC
  • Publication number: 20220165194
    Abstract: An image dividing circuit includes an input interface circuit that receives input image data configured by a total number of horizontal pixels HT, an image data dividing circuit that divides the input image data into first to n-th output image data, and an output interface circuit that includes output circuits for first to n-th channels that output the first to n-th output image data. The parameter n is an integer greater than or equal to 3, and the parameter HT is not an integer multiple of the parameter n. An output circuit for an i-th channel outputs i-th output image data in which at least one of the total number of horizontal pixels and the total number of vertical lines in the i-th channel has been variably adjusted. The parameter i is an integer greater than or equal to 1 but smaller than or equal to n.
    Type: Application
    Filed: November 24, 2021
    Publication date: May 26, 2022
    Inventor: Yasutoshi AKIBA
  • Publication number: 20220101487
    Abstract: A circuit apparatus includes a memory unit and a warp processing unit. The memory unit stores a warp object image. The warp processing unit performs warp processing on the warp object image and generates a display image displayed in a display area. The warp processing unit performs the warp processing on an image of a first view object of the warp object image based on a first warp parameter for vibration correction and distortion correction. Further, the warp processing unit performs the warp processing on an image of a second view object of the warp object image based on a second warp parameter for the distortion correction.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 31, 2022
    Inventors: Yasutoshi AKIBA, Kumar Anandabairavasamy ANAND, Jeffrey ERIC
  • Patent number: 11180026
    Abstract: A circuit device includes an image processing circuit and a comparison circuit. The image processing circuit performs a first mapping process and a first rotation process on an input image to generate an image for a head up display. The image processing circuit performs, on an image, a second mapping process that is a reverse mapping process of the first mapping process and a second rotation process that is a reverse rotation process of the first rotation process to generate an image. The comparison circuit performs a comparison between the image and the image and outputs a result of the comparison as information for detecting an error in the image.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 23, 2021
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Kumar Anandabairavasamy Anand, Wittmeir Manfred, Jeffrey Eric, Tetsuo Kawamoto, Yasutoshi Akiba
  • Patent number: 11010866
    Abstract: A circuit device (100) includes a coordinate transform circuit (20) and a mapping processing circuit (30). The coordinate transform circuit (20) performs coordinate transformation from an input coordinate (IXY1) to an output coordinate (QXY1). The mapping processing circuit (30) generates a second image (IMG2) to be displayed in a display panel for displaying an image in a curved screen display by performing mapping processing on a first image (IMG1) that is input based on the output coordinate (QXY1). The coordinate transform circuit (20) performs the coordinate transformation from the input coordinate (IXY1) to the output coordinate (QXY1) by performing computation processing using a second or more order polynomial representing the coordinate transformation.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: May 18, 2021
    Inventors: Jeffrey Eric, Kumar Anandabairavasamy Anand, Yasutoshi Akiba
  • Publication number: 20200342567
    Abstract: A circuit device (100) includes a coordinate transform circuit (20) and a mapping processing circuit (30). The coordinate transform circuit (20) performs coordinate transformation from an input coordinate (IXY1) to an output coordinate (QXY1). The mapping processing circuit (30) generates a second image (IMG2) to be displayed in a display panel for displaying an image in a curved screen display by performing mapping processing on a first image (IMG1) that is input based on the output coordinate (QXY1). The coordinate transform circuit (20) performs the coordinate transformation from the input coordinate (IXY1) to the output coordinate (QXY1) by performing computation processing using a second or more order polynomial representing the coordinate transformation.
    Type: Application
    Filed: April 28, 2020
    Publication date: October 29, 2020
    Inventors: Jeffrey ERIC, Kumar Anandabairavasamy ANAND, Yasutoshi AKIBA
  • Publication number: 20200198468
    Abstract: A circuit device includes an image processing circuit and a comparison circuit. The image processing circuit performs a first mapping process and a first rotation process on an input image to generate an image for a head up display. The image processing circuit performs, on an image, a second mapping process that is a reverse mapping process of the first mapping process and a second rotation process that is a reverse rotation process of the first rotation process to generate an image. The comparison circuit performs a comparison between the image and the image and outputs a result of the comparison as information for detecting an error in the image.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kumar anandabairavasamy ANAND, Wittmeir MANFRED, Jeffrey ERIC, Tetsuo KAWAMOTO, Yasutoshi AKIBA
  • Publication number: 20200201035
    Abstract: A circuit device 100 includes an error detection circuit 110 and a processing circuit 120. The error detection circuit 110 obtains a glare index value, which is an index value indicating glare of a head-up display, based on image data IMD for head-up display. The error detection circuit 110 determines whether or not a glare index value has exceeded a first threshold value, and when the glare index value exceeds the first threshold value, detects occurrence of a first glare error. When occurrence of a first glare error is detected, the processing circuit 120 performs processing corresponding to the first glare error.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 25, 2020
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Kumar Anandabairavasamy ANAND, Wittmeir MANFRED, Jeffrey ERIC, Tetsuo KAWAMOTO, Yasutoshi AKIBA