Patents by Inventor Yasutsugu Usami

Yasutsugu Usami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010021019
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: September 13, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi
  • Publication number: 20010019411
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: September 6, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Publication number: 20010015805
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 23, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi
  • Publication number: 20010011706
    Abstract: Inspection method, apparatus, and system for a circuit pattern, in which when various conditions which are necessary in case of inspecting a fine circuit pattern by using an image formed by irradiating white light, a laser beam, or a charged particle beam are set, its operating efficiency can be improved. An inspection target region of an inspection-subject substrate is displayed, and a designated map picture plane and an image of an optical microscope or an electron beam microscope of a designated region are displayed in parallel, thereby enabling a defect distribution and a defect image to be simultaneously seen. Item names of inspecting conditions and a picture plane to display, input, or instruct the contents of the inspecting conditions are integrated, those contents are overlapped to the picture plane and layer-displayed, and all of the item names are displayed in parallel in a tab format in the upper portion of the picture plane of the contents.
    Type: Application
    Filed: April 11, 2001
    Publication date: August 9, 2001
    Inventors: Yasuhiko Nara, Kazuhisa Machida, Mari Nozoe, Hiroshi Morioka, Yasutsugu Usami, Takashi Hiroi, Kohichi Hayakawa, Maki Ito
  • Patent number: 6236057
    Abstract: A method and apparatus for inspecting a pattern, a first image of a first area on a sample is acquired by imaging the first area formed as a first pattern, and the first image is memorized. A second image of a second area on the sample is acquired by imaging the second area formed as a second pattern which is to be the same as the first pattern. A defect of the first pattern is detected by acquiring a differential image between the first image and the second image. The detection of the defect includes processing the differential image by using information of brightness corresponding to both of the first image and the second image.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: May 22, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Chie Shishido, Takashi Hiroi, Haruo Yoda, Masahiro Watanabe, Asahiro Kuni, Maki Tanaka, Takanori Ninomiya, Hideaki Doi, Shunji Maeda, Mari Nozoe, Hiroyuki Shinoda, Atsuko Takafuji, Aritoshi Sugimoto, Yasutsugu Usami
  • Patent number: 6172363
    Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: January 9, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
  • Patent number: 6107637
    Abstract: An electronic beam type exposure or inspection or measurement apparatus and method including an electron optical system, an electron beam image detection optical system for detecting a secondary electron beam image generated from an inspected object by electron beams irradiated from the electron optical system, and an optical height detection apparatus for optically detecting a height of a surface in an area on the inspected object. A focus controller is provided for calculating a focus control current or a focus control voltage based on a correction parameter between a height of a surface on the inspected object and a focus control current or a focus control voltage and supplying the same to an objective lens of the electron optical system in such a manner that an electron beam is focused on the inspected object in a properly- focused state.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: August 22, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Masahiro Watanabe, Takashi Hiroi, Maki Tanaka, Hiroyuki Shinada, Yasutsugu Usami
  • Patent number: 6087673
    Abstract: In a method of inspecting a defect and an apparatus thereof, an allowable range for a gradation value of a difference image is determined for each pixel from one pixel or less of position shift quantity between two images to be compared, a variation rate in a local gradation value of an image, and a representative value of the local gradation value. Then, by comparing the gradation value of the difference image with the allowable range determined for each pixel, a pixel, on which the gradation value of the difference image is within the allowable range, is judged to be an non-defective candidate and a pixel, on which the gradation value of the difference image is beyond the allowable range, is judged to be a defective candidate.
    Type: Grant
    Filed: May 20, 1998
    Date of Patent: July 11, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Chie Shishido, Takashi Hiroi, Haruo Yoda, Masahiro Watanabe, Asahiro Kuni, Maki Tanaka, Takanori Ninomiya, Hideaki Doi, Shunji Maeda, Mari Nozoe, Hiroyuki Shinoda, Atsuko Takafuji, Aritoshi Sugimoto, Yasutsugu Usami
  • Patent number: 5478195
    Abstract: Apparatus for processing semiconductor wafers includes a load lock chamber with a first gate valve and a second gate valve so as to load and unload cassettes through the first gate valve, and to convey the wafers from the load lock chamber to a plurality of processing chambers through respective second valves. The load lock chamber is provided with a turntable which holds the plurality of cassettes. The turntable conveys each of the cassettes in front of respective ones of the second valves.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: December 26, 1995
    Assignee: Hitachi, Ltd.
    Inventor: Yasutsugu Usami