Patents by Inventor Yasuyoshi Kunimatsu

Yasuyoshi Kunimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5818106
    Abstract: A semiconductor device which includes a ceramic package main body, a semiconductor element and a closure for sealing the semiconductor element in the package. A capacitor is formed on an upper or lower surface of the closure. The capacitor has a dielectric film interposed between a pair of electrode films. The dielectric film includes a ceramic filler and an amorphous glass. The closure and the package main body are sealed. A terminal formed in the package main body and the electrode film of the capacitor are connected electrically. High-density packaging on a substrate can be achieved. High strength of the closure itself can be maintained. Thermal stress developed in the closure itself, or the conjugated portion between the closure and the package main body, can be suppressed. Reliability of a sealed structure in the semiconductor device for a long period of time can be increased.
    Type: Grant
    Filed: November 29, 1995
    Date of Patent: October 6, 1998
    Assignee: Kyocera Corporation
    Inventor: Yasuyoshi Kunimatsu
  • Patent number: 5767564
    Abstract: A semiconductor device having a semiconductor element mounted on an insulating substrate and a decoupling capacitor provided on the semiconductor element. The semiconductor device minimizes the occurrence of switching noise. The semiconductor device comprises an insulating substrate, a semiconductor element mounted on said insulating substrate, and a decoupling capacitor which is joined to the upper surface of said semiconductor element and is electrically connected to said semiconductor element, wherein said decoupling capacitor has a coefficient of thermal expansion close to the coefficient of thermal expansion of said semiconductor element, and is electrically connected to said semiconductor element by soldering and is further secured to said semiconductor element.
    Type: Grant
    Filed: July 12, 1996
    Date of Patent: June 16, 1998
    Assignee: Kyocera Corporation
    Inventors: Yasuyoshi Kunimatsu, Akira Furuzawa, Akifumi Sata
  • Patent number: 5763059
    Abstract: In a circuit board obtained by providing a metallized layer of wiring on the surface or interior of an insulation substrate, the insulation substrate is, for example, a multi-layer circuit board or a package for semiconductor element, the insutating substrate obtained from a sintered body having a linear expansion coefficient of 8 to 18 ppm/.degree. C. at 40.degree. to 400.degree. C. which is prepared by sintering a molded body containing 20 to 80% of a glass having a liner expansion coefficient of 6 to 18 ppm/.degree. C. at 40.degree. to 400.degree. C. and 80 to 20% of a filler having a linear expansion coefficient of at least 6 ppm/.degree. C.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: June 9, 1998
    Assignee: Kyocera Corporation
    Inventors: Kouichi Yamaguchi, Noriaki Hamada, Hideto Yonekura, Takeshi Kubota, Yasuyoshi Kunimatsu, Yasuhide Tami, Masahiko Higashi, Yohji Furukubo