Patents by Inventor Yasuyuki Hashimoto
Yasuyuki Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955390Abstract: A semiconductor wafer evaluation method includes acquiring a reflection image as a bright-field image by receiving reflected light which is obtained when irradiating one surface side of a semiconductor wafer to be evaluated with light; acquiring a scattered image as a dark-field image by receiving scattered light which is obtained when irradiating the surface side of the semiconductor wafer with light; and obtaining a distance between a bright zone that is observed in the reflection image and a bright zone that is observed in the scattered image. The semiconductor wafer to be evaluated is a semiconductor wafer in which a chamfered surface is formed in a wafer outer peripheral edge section, and the method includes evaluating a shape of a boundary part between a main surface on the surface side irradiated with the light of the semiconductor wafer to be evaluated and a chamfered surface adjacent to the main surface.Type: GrantFiled: January 7, 2019Date of Patent: April 9, 2024Assignee: SUMCO CORPORATIONInventors: Takahiro Nagasawa, Yasuyuki Hashimoto, Hirotaka Kato
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Patent number: 11948789Abstract: A manufacturing method of a wafer includes a first and a second resin-application grinding step, and a third surface-grinding step. The first step includes: a first formation step of forming a first coating layer; a first surface-grinding step of placing the wafer so that the first coating layer contacts a reference surface of a table and surface-grinding a first surface of the wafer; and a first removal step of removing the first coating layer. The second step includes: a second formation step of forming a second coating layer; a second surface-grinding step of placing the wafer so that the second coating layer contacts the reference surface and surface-grinding the second surface; and a second removal step of removing the second coating layer. In the third step, the wafer is placed so that the last surface-ground surface contacts the reference surface and a surface opposite the contacted surface is surface-ground.Type: GrantFiled: February 21, 2018Date of Patent: April 2, 2024Assignee: SUMCO CORPORATIONInventors: Toshiyuki Tanaka, Yasuyuki Hashimoto
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Publication number: 20200411391Abstract: A semiconductor wafer evaluation method includes acquiring a reflection image as a bright-field image by receiving reflected light which is obtained when irradiating one surface side of a semiconductor wafer to be evaluated with light; acquiring a scattered image as a dark-field image by receiving scattered light which is obtained when irradiating the surface side of the semiconductor wafer with light; and obtaining a distance between a bright zone that is observed in the reflection image and a bright zone that is observed in the scattered image. The semiconductor wafer to be evaluated is a semiconductor wafer in which a chamfered surface is formed in a wafer outer peripheral edge section, and the method includes evaluating a shape of a boundary part between a main surface on the surface side irradiated with the light of the semiconductor wafer to be evaluated and a chamfered surface adjacent to the main surface.Type: ApplicationFiled: January 7, 2019Publication date: December 31, 2020Applicant: SUMCO CORPORATIONInventors: Takahiro NAGASAWA, Yasuyuki HASHIMOTO, Hirotaka KATO
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Publication number: 20200381243Abstract: A manufacturing method of a wafer includes a first and a second resin-application grinding step, and a third surface-grinding step. The first step includes: a first formation step of forming a first coating layer; a first surface-grinding step of placing the wafer so that the first coating layer contacts a reference surface of a table and surface-grinding a first surface of the wafer; and a first removal step of removing the first coating layer. The second step includes: a second formation step of forming a second coating layer; a second surface-grinding step of placing the wafer so that the second coating layer contacts the reference surface and surface-grinding the second surface; and a second removal step of removing the second coating layer. In the third step, the wafer is placed so that the last surface-ground surface contacts the reference surface and a surface opposite the contacted surface is surface-ground.Type: ApplicationFiled: February 21, 2018Publication date: December 3, 2020Applicant: SUMCO CORPORATIONInventors: Toshiyuki TANAKA, Yasuyuki HASHIMOTO
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Publication number: 20180297168Abstract: Disclosed is a semiconductor wafer processing method wherein, a thin disc-like wafer is manufactured by slicing a semiconductor single crystal ingot (slicing step), a planarized coating layer is formed by applying a curable material to the whole first surface of the wafer (coating layer forming step), and the coating layer is cured (coating layer curing step). A wafer second surface on the reverse side of the first surface is flatly grind by means of a grinding apparatus, the coating layer is removed from the first surface of the wafer. Furthermore, the first surface of the wafer is flatly ground by means of the grinding apparatus. The surface height of the first surface of the wafer after the slicing step and before the coating layer forming step is subjected to frequency analysis, and the coating layer forming step and the coating layer curing step are repeated a plurality of times.Type: ApplicationFiled: October 3, 2016Publication date: October 18, 2018Applicant: SUMCO CORPORATIONInventors: Toshiyuki TANAKA, Yasuyuki HASHIMOTO
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Patent number: 9958063Abstract: A hydraulic control device controls hydraulic pressure supplied to a continuously variable transmission. The hydraulic control device includes a pressure regulating valve, a solenoid valve configured to control the pilot pressure, line pressure control means, and hydraulic control means. The pressure regulating valve includes an input port to which line pressure is input, an output port configured to supply an oil chamber of a second pulley with a second pulley pressure, a drain port configured to discharge the second pulley pressure from the oil chamber, and a spool moving according to pilot pressure to regulate the second pulley pressure. The line pressure control means is configured to control the line pressure on the basis of the second pulley pressure and first pulley pressure of first pulley. The hydraulic control means is configured to temporarily change the pilot pressure from set pressure to configure the line pressure identical to the second pulley pressure.Type: GrantFiled: February 16, 2015Date of Patent: May 1, 2018Assignee: JATCO LtdInventors: Yasuyuki Hashimoto, Seiichiro Takahashi, Tomoaki Honma, Tomoaki Kabe, Nobuhiko Morifuji, Nobuhide Kato, Hitoshi Goka, Koichi Sugita
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Patent number: 9881783Abstract: In a wafer processing method by which, by using, as a reference surface, a flat surface obtained by applying a curable material to the whole of one surface of a wafer obtained by slicing a semiconductor single-crystal ingot by using a wire saw apparatus, surface grinding is performed on the other surface of the wafer and surface grinding is performed on the one surface of the wafer by using the other surface of the wafer subjected to surface grinding as a reference surface, both surfaces of the wafer are planarized at the same time immediately after the wafer is obtained by slicing.Type: GrantFiled: February 4, 2014Date of Patent: January 30, 2018Assignee: SUMCO CORPORATIONInventors: Toshiyuki Tanaka, Yasuyuki Hashimoto, Tomohiro Hashii
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Publication number: 20160356380Abstract: A hydraulic control device controls hydraulic pressure supplied to a continuously variable transmission. The hydraulic control device includes a pressure regulating valve, a solenoid valve configured to control the pilot pressure, line pressure control means, and hydraulic control means. The pressure regulating valve includes an input port to which line pressure is input, an output port configured to supply an oil chamber of a second pulley with a second pulley pressure, a drain port configured to discharge the second pulley pressure from the oil chamber, and a spool moving according to pilot pressure to regulate the second pulley pressure. The line pressure control means is configured to control the line pressure on the basis of the second pulley pressure and first pulley pressure of first pulley. The hydraulic control means is configured to temporarily change the pilot pressure from set pressure to configure the line pressure identical to the second pulley pressure.Type: ApplicationFiled: February 16, 2015Publication date: December 8, 2016Applicant: JATCO LtdInventors: Yasuyuki HASHIMOTO, Seiichiro TAKAHASHI, Tomoaki HONMA, Tomoaki KABE, Nobuhiko MORIFUJI, Nobuhide KATO, Hitoshi GOKA, Koichi SUGITA
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Patent number: 9324558Abstract: A surface of a semiconductor wafer is subjected to high flattening processing. A resin application and grinding step is repeatedly carried out, the step including determining as a reference surface a flat surface obtained by applying a curable material to one entire surface of a wafer sliced out from a semiconductor single crystal ingot with the use of a wire saw apparatus and performing surface grinding with respect to the other surface of the wafer, and determining as a reference surface the other surface of the wafer subjected to the surface grinding and performing the surface grinding with respect to the one surface of the wafer.Type: GrantFiled: June 20, 2014Date of Patent: April 26, 2016Assignee: SUMCO CORPORATIONInventors: Toshiyuki Tanaka, Yasuyuki Hashimoto, Tomohiro Hashii
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Patent number: 9190267Abstract: Provided is an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.Type: GrantFiled: November 10, 2011Date of Patent: November 17, 2015Assignee: SUMCO CorporationInventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto
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Publication number: 20150303049Abstract: In a wafer processing method by which, by using, as a reference surface, a flat surface obtained by applying a curable material to the whole of one surface of a wafer obtained by slicing a semiconductor single-crystal ingot by using a wire saw apparatus, surface grinding is performed on the other surface of the wafer and surface grinding is performed on the one surface of the wafer by using the other surface of the wafer subjected to surface grinding as a reference surface, both surfaces of the wafer are planarized at the same time immediately after the wafer is obtained by slicing.Type: ApplicationFiled: February 4, 2014Publication date: October 22, 2015Applicant: SUMCO CORPORATIONInventors: Toshiyuki TANAKA, Yasuyuki HASHIMOTO, Tomohiro HASHII
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Publication number: 20150004799Abstract: A surface of a semiconductor wafer is subjected to high flattening processing. A resin application and grinding step is repeatedly carried out, the step including determining as a reference surface a flat surface obtained by applying a curable material to one entire surface of a wafer sliced out from a semiconductor single crystal ingot with the use of a wire saw apparatus and performing surface grinding with respect to the other surface of the wafer, and determining as a reference surface the other surface of the wafer subjected to the surface grinding and performing the surface grinding with respect to the one surface of the wafer.Type: ApplicationFiled: June 20, 2014Publication date: January 1, 2015Inventors: Toshiyuki TANAKA, Yasuyuki HASHIMOTO, Tomohiro HASHII
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Patent number: 8298437Abstract: An alkali etching liquid for a silicon wafer that includes an aqueous solution of potassium hydroxide, and from 0.1 g/L to 0.5 g/L of diethylene triamine pentaacetic acid. Furthermore, the Fe concentration of the aqueous solution of potassium hydroxide is no more than 50 ppb. An etching method that including a step of etching a silicon wafer with a resistivity of no more than 1 ?·cm using the etching liquid.Type: GrantFiled: October 8, 2009Date of Patent: October 30, 2012Assignee: Sumco CorporationInventors: Takahisa Nakashima, Makoto Takemura, Yasuyuki Hashimoto
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Publication number: 20120056307Abstract: Provided is an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.Type: ApplicationFiled: November 10, 2011Publication date: March 8, 2012Applicant: SUMCO CORPORATIONInventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto
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Patent number: 8080106Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.Type: GrantFiled: July 20, 2009Date of Patent: December 20, 2011Assignee: Sumco CorporationInventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto
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Patent number: 7902039Abstract: A method for manufacturing a silicon wafer is characterized by performing one or both of grinding and polishing to a thin discoid silicon wafer to give bowl-shaped warpage that is concave at a central part to a wafer surface. One main surface of the thin discoid silicon wafer is adsorbed and held, and one or both of grinding and polishing are performed to the other main surface to fabricate a convex wafer whose thickness is increased from a wafer outer periphery toward a wafer center or fabricate a concave wafer whose thickness is reduced from the wafer outer periphery toward the wafer center. Then, the other main surface is adsorbed and held to protrude the center or the periphery of the one main surface side based on elastic deformation. One or both of grinding and polishing are carried out with respect to the one main surface to flatten the main surface, and adsorption and holding are released to give bowl-shaped warpage that is concave at the central part to the other main surface or the one main surface.Type: GrantFiled: November 28, 2007Date of Patent: March 8, 2011Assignee: Sumco CorporationInventors: Shinichi Tomita, Masao Yoshimuta, Yasuyuki Hashimoto, Akira Nakashima
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Patent number: 7781313Abstract: A method for manufacturing a silicon wafer is characterized by performing one or both of grinding and polishing to a thin discoid silicon wafer to give bowl-shaped warpage that is concave at a central part to a wafer surface. One main surface of the thin discoid silicon wafer is adsorbed and held, and one or both of grinding and polishing are performed to the other main surface to fabricate a convex wafer whose thickness is increased from a wafer outer periphery toward a wafer center or fabricate a concave wafer whose thickness is reduced from the wafer outer periphery toward the wafer center. Then, the other main surface is adsorbed and held to protrude the center or the periphery of the one main surface side based on elastic deformation. One or both of grinding and polishing are carried out with respect to the one main surface to flatten the main surface, and adsorption and holding are released to give bowl-shaped warpage that is concave at the central part to the other main surface or the one main surface.Type: GrantFiled: September 1, 2009Date of Patent: August 24, 2010Assignee: Sumco CorporationInventors: Shinichi Tomita, Masao Yoshimuta, Yasuyuki Hashimoto, Akira Nakashima
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Publication number: 20100130289Abstract: A damper mechanism 4 has an input rotary body 2, a hub flange 6, a splined hub 3, a third friction washer 60, a bushing 70, and an output plate 90. The third friction washer 60 is non-rotatably mounted on the hub flange 6 with respect to the hub flange 6, and has a friction member that contacts the input rotary body 2 in the axial direction. The bushing 70 is axially disposed between the hub flange 6 and the third friction washer 60, and is mounted on the hub flange 6 and the third friction washer 60 to be incapable of rotation with respect to the third friction washer 60. The output plate 90 is disposed between the third friction washer 60 and the bushing 70 in the axial direction, and is supported by the splined hub 3 to be capable of rotating integrally with the splined hub 3.Type: ApplicationFiled: May 28, 2008Publication date: May 27, 2010Applicant: EXEDY CORPORATIONInventors: Hiroshi Uehara, Yasuyuki Hashimoto, Hideki Hashimoto, Yoshinari Yoshimura
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Publication number: 20100032806Abstract: Provided are an epitaxial silicon wafer in which the warping is reduced by rendering a cross-sectional form of a silicon wafer for epitaxial growth into an adequate form as compared with the conventional one, and a production method thereof. An epitaxial silicon wafer comprising a silicon wafer for epitaxial growth and an epitaxial layer is characterized in that the epitaxial layer is formed on a silicon wafer for epitaxial growth having a cross-sectional form satisfying a relation of a given expression.Type: ApplicationFiled: July 20, 2009Publication date: February 11, 2010Applicant: SUMCO CORPORATIONInventors: Takayuki Kihara, Kazushige Takaishi, Yasuyuki Hashimoto
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Publication number: 20100025624Abstract: An alkali etching liquid for a silicon wafer that includes an aqueous solution of potassium hydroxide, and from 0.1 g/L to 0.5 g/L of diethylene triamine pentaacetic acid. Furthermore, the Fe concentration of the aqueous solution of potassium hydroxide is no more than 50 ppb. An etching method that including a step of etching a silicon wafer with a resistivity of no more than 1 ?·cm using the etching liquid.Type: ApplicationFiled: October 8, 2009Publication date: February 4, 2010Applicant: SUMCO CORPORATIONInventors: Takahisa NAKASHIMA, Makoto Takemura, Yasuyuki Hashimoto