Patents by Inventor Yasuyuki Hirasaki

Yasuyuki Hirasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit including built-in self test circuit to test memory and memory test method
    Patent number: 7876633
    Abstract: An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: January 25, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuyuki Hirasaki, Yoshitaka Aoki, Katsumi Shinbo
  • Integrated circuit including Built-In Self Test circuit to test memory and memory test method
    Publication number: 20090238018
    Abstract: An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 24, 2009
    Applicant: NEC Electronics Corporation
    Inventors: Yasuyuki Hirasaki, Yoshitaka Aoki, Katsumi Shinbo