Abstract: An examination schedule management unit manages an examination schedule of a plurality of endoscopic examinations, including an examination room where an endoscopic examination is to be performed, information on scheduled examination start time, that on scheduled examination end time, and examination type information on an examination content of an endoscopic examination. A cleaning schedule management unit manages a cleaning schedule of a plurality of endoscopes, including a cleaning machine, information on scheduled cleaning start time, and that on scheduled cleaning end time.

Abstract: An apparatus, which controls the temperature of a secondary battery formed by combination of a plurality of single cells or a plurality of battery modules each made by series connection of multiple single cells, prevents variations in the temperature or voltage of the single cells or the battery modules, which could otherwise be caused when the secondary battery is heated. A temperature control section controls the quantity of heat by means of which a heater heats a secondary battery formed by combination of a plurality of battery modules made by series connection of multiple single cells. The temperature control section detects a rate of temporal changes in an open circuit voltage of the secondary battery. When a detected rate of temporal changes in open circuit voltage has exceeded a predetermined threshold voltage value, the heater is controlled to thus diminish the quantity of heat used for heating the secondary battery.

Abstract: An internal nonvolatile memory contains a program to be executed during a rewrite operation mode. During the rewrite operation mode a CPU core writes received rewrite data to an external nonvolatile memory according to a program in the internal nonvolatile memory. A first selector circuit transmits a first chip select signal to the external nonvolatile memory when a mode signal indicates a normal operation mode, and transmits the first chip select signal to the internal nonvolatile memory when the mode signal indicates the rewrite operation mode. Since the activation of the internal nonvolatile memory is inhibited during the normal operation mode, it is possible to prevent erroneous execution of the program in the internal nonvolatile memory during the normal operation mode, and to prevent data rewrite to the external nonvolatile memory.

Abstract: An apparatus, which controls the temperature of a secondary battery formed by combination of a plurality of single cells or a plurality of battery modules each made by series connection of multiple single cells, prevents variations in the temperature or voltage of the single cells or the battery modules, which could otherwise be caused when the secondary battery is heated. A temperature control section controls the quantity of heat by means of which a heater heats a secondary battery formed by combination of a plurality of battery modules made by series connection of multiple single cells. The temperature control section detects a rate of temporal changes in an open circuit voltage of the secondary battery. When a detected rate of temporal changes in open circuit voltage has exceeded a predetermined threshold voltage value, the heater is controlled to thus diminish the quantity of heat used for heating the secondary battery.

Abstract: A system for DMA transfer includes a CPU core having a DMA function, a first macro including a FIFO having a first bit width, and a second macro including a FIFO having a second bit width narrower than the first bit width, wherein an address signal fixing circuit is provided, and is configured to fix a portion of an address for accessing from the CPU core the FIFO of the second macro.

Abstract: An external port control register of an input/output port outputs a setting value signal indicating a setting value in order that either a general-purpose input/output port function or a functional block input/output pin function is set to an external pin. A selector of the input/output port connects either a general output path or an output path of a functional block receiving a functional block input signal, to the external pin according to the setting value signal. An interrupting circuit interrupts the supply of the functional block input signal to the functional block when the setting value signal indicates the general-purpose input/output port function. Consequently, any register circuit designating whether to enable or disable the supply of the functional block input signal to the functional block need not be provided in particular, which can eliminate the need for a redundant setting process in switching the pin function of the external pin.

Abstract: An internal nonvolatile memory contains a program to be executed during a rewrite operation mode. During the rewrite operation mode a CPU core writes received rewrite data to an external nonvolatile memory according to a program in the internal nonvolatile memory. A first selector circuit transmits a first chip select signal to the external nonvolatile memory when a mode signal indicates a normal operation mode, and transmits the first chip select signal to the internal nonvolatile memory when the mode signal indicates the rewrite operation mode. Since the activation of the internal nonvolatile memory is inhibited during the normal operation mode, it is possible to prevent erroneous execution of the program in the internal nonvolatile memory during the normal operation mode, and to prevent data rewrite to the external nonvolatile memory.

Abstract: A direct memory access controller for transferring data from a transfer source memory region to a transfer destination memory region, comprises: a transfer source address calculation unit which has transfer source address registers corresponding to a plurality of channels and which generates a transfer source address whenever data transfer is performed; a transfer destination address calculation unit which has transfer destination address registers corresponding to the plurality of channels and which generates a transfer destination address whenever data transfer is performed. The transfer source or destination address calculation unit calculates upon data transfer a transfer source or destination address for the following data transfer from the initially set transfer source or destination address and the transfer source or destination address register retains the initially set transfer source or destination address.

Abstract: A direct memory access controller for transferring data from a transfer source memory region to a transfer destination memory region, comprises: a transfer source address calculation unit which has transfer source address registers corresponding to a plurality of channels and which generates a transfer source address whenever data transfer is performed; a transfer destination address calculation unit which has transfer destination address registers corresponding to the plurality of channels and which generates a transfer destination address whenever data transfer is performed. The transfer source or destination address calculation unit calculates upon data transfer a transfer source or destination address for the following data transfer from the initially set transfer source or destination address and the transfer source or destination address register retains the initially set transfer source or destination address.

Abstract: A microcontroller is provided which has a structure installable in a conventional circuit configuration including a cache memory without any modification and allows a central processing unit to access the cache memory in one cycle. The microcontroller includes a central processing unit, a bus control unit connected to the central processing unit through an instruction bus and a data bus provided independently, a memory interface circuit receiving the instruction bus and a memory bus extending from the bus control unit and controlling an instruction access via the instruction bus and a data access via the memory bus, and a memory subjected to the instruction access and the data access via said memory interface circuit. Thus, the instruction access to the memory can be performed in the same manner as that of an instruction access to an instruction cache memory. Thus, the cache hit surely occurs for each instruction access, so that the access efficiency can be enhanced.

Abstract: A microcontroller is provided which has a structure installable in a conventional circuit configuration including a cache memory without any modification and allows a central processing unit to access the cache memory in one cycle. The microcontroller includes a central processing unit, a bus control unit connected to the central processing unit through an instruction bus and a data bus provided independently, a memory interface circuit receiving the instruction bus and a memory bus extending from the bus control unit and controlling an instruction access via the instruction bus and a data access via the memory bus, and a memory subjected to the instruction access and the data access via said memory interface circuit. Thus, the instruction access to the memory can be performed in the same manner as that of an instruction access to an instruction cache memory. Thus, the cache hit surely occurs for each instruction access, so that the access efficiency can be enhanced.