Abstract: A method for refolding an antibody, a process for producing a refolded antibody, a refolded antibody, and uses thereof are provided. A method for refolding an antibody in a liquid phase comprises the steps of denaturing an inactive antibody binding directly or through a linker to a peptide, the peptide having an isoelectric point lower than the isoelectric point of the inactive antibody, and dispersing in a liquid phase the peptide-binding inactive antibody denatured in the step above. Also provided is a process for producing a refolded antibody.

Abstract: A method for refolding an antibody, a process for producing a refolded antibody, a refolded antibody, and uses thereof are provided. A method for refolding an antibody in a liquid phase comprises the steps of denaturing an inactive antibody binding directly or through a linker to a peptide, the peptide having an isoelectric point lower than the isoelectric point of the inactive antibody, and dispersing in a liquid phase the peptide-binding inactive antibody denatured in the step above. Also provided is a process for producing a refolded antibody.

Abstract: An apparatus for manufacturing an absorbent article, the absorbent article including an absorbent core and a sheet whereon the absorbent core is placed, including: (A) a transportation section transporting in a transport direction the sheet whereon the absorbent core is placed; and (B) a bending section bending the sheet, in an intersecting direction that intersects the transport direction, while the transportation section is transporting the sheet, (C) a first part of the sheet, positioned in a bending point where the bending section bends in the intersecting direction the sheet, is distant in the intersecting direction from the absorbent core, (D) a second part of the sheet positioned on an opposite side of the first part from the absorbent core, in the intersecting direction, collapses onto a third part positioned on the absorbent core side from the first part, in the intersecting direction, by the bending section bending the sheet at the bending point, (E) the bending section further including a regulatio

Abstract: A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.

Abstract: In a DPLL circuit, when the size of a data value which is output from a data latch circuit and should be naturally set in a 11-bit down-counter becomes equal to or more than 12 bits, an overflow preventing circuit substitutes the 11-bit data for the data value.

Abstract: A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.

Abstract: A semiconductor integrated circuit device for controlling an external output transistor is provided. The semiconductor integrated circuit device comprises: a first power supply circuit including an output circuit and providing a first series regulator in cooperation with the output external transistor; and a plurality of terminals. The plurality of terminals includes a control signal output terminal and high and low electric potential side power supply terminals for supplying electric power to the first power supply circuit. At least one of the high and low electric potential side power supply terminals is arranged adjacent to the control signal output terminal and defined as a first terminal. Short-circuiting between the control signal output terminal and the first terminal causes the external output transistor to switch into an off state.

Abstract: In a DPLL circuit, when the size of a data value which is output from a data latch circuit and should be naturally set in a 11-bit down-counter becomes equal to or more than 12 bits, an overflow preventing circuit substitutes the 11-bit data for the data value.

Abstract: A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.

Abstract: A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is equal to or higher than a reset voltage for the logic circuit. The second determining circuit operates with the first voltage and determines whether the first voltage is equal to or higher than a minimum operating voltage as a guarantee voltage for an operation of the first determining circuit. The reset signal generating circuit outputs a reset signal for resetting the logic circuit and the RAM, when the first voltage is lower than the minimum operating voltage and the second voltage is lower than the reset voltage.

Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.

Abstract: Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

Abstract: Noise current flowing to the outside of an IC (1) with respect to the capacitance value and arrangement location of a bypass capacitor (4) is calculated on the basis of the impedance of current paths (P1, P2) passing via a bypass capacitor (4) at the outside of the IC (1) and the impedance of the inside of IC (1) when viewed from power supply terminals (2, 3) of the IC (1). The capacitance value and arrangement location of the bypass capacitor (4) are determined on the basis of the calculation result.

Abstract: A microcomputer includes a plurality of operation mode selecting terminals to which data for selecting plural operation modes are set. The plurality of operation mode selecting terminals is designed so as to be usable as general-purpose input terminals or output terminals. A decoder decodes the data set to the plurality of operation mode selecting terminals and outputting a mode signal for switching an internal function in accordance with a selected operation mode. A timing signal output unit outputs to the decoder a timing signal for making the decoder execute a decode operation. The timing signal output unit outputs the timing signal when at least one of power-on-reset and an externally controlled reset is varied from an active state to an inactive state.

Abstract: In a clamp circuit device, reference voltages are set up by a series circuit of an FET, a resistor and an FET. Gate potentials of FETs are set up by performing addition and subtraction of these reference voltages and a reference voltage generated by a bandgap reference circuit, respectively. The clamp circuit device is constructed by connecting together a source of the one FET with its drain connected with the power supply and a source of the other FET with its drain connected with the ground to an input terminal of a control IC unit. Thus, an input voltage is clamped to [V4+Vtp] when an excessive voltage of positive polarity is applied to an input terminal, and the input voltage is clamped to [V5?Vtn] when an excessive voltage of negative polarity is applied.

Abstract: Integrated circuit device includes: a wiring; a clock signal output circuit including a ring oscillator; an internal circuit; an internal power supply generation circuit for supplying an electric power to the clock signal output circuit and to the internal circuit on the basis of a power supplied from an external circuit; and a capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the ring oscillator through the wiring connecting between the internal power supply generation circuit and the capacitor connection terminal. The internal power supply generation circuit supplies the electric power to the internal circuit through the wiring connecting to the capacitor connection terminal.

Abstract: Noise current flowing to the outside of an IC (1) with respect to the capacitance value and arrangement location of a bypass capacitor (4) is calculated on the basis of the impedance of current paths (P1, P2) passing via a bypass capacitor (4) at the outside of the IC (1) and the impedance of the inside of IC (1) when viewed from power supply terminals (2, 3) of the IC (1). The capacitance value and arrangement location of the bypass capacitor (4) are determined on the basis of the calculation result.

Abstract: A common power source line has first power supply points and second power supply points. The first power supply points are provided for supplying electric power to buffer circuits of low-frequency signal pads, while the second power supply points are provided for buffer circuits of high-frequency signal pads. A wiring distance from a power source pad to the second power supply points as well as a wiring distance from the first power supply points to the second power supply points are set to be relatively long in an overall wiring arrangement on a chip.

Abstract: A plurality of bypass capacitors are associated with a plurality of circuit blocks involved in a microcomputer. Each bypass capacitor is disposed between a power input terminal of a corresponding circuit block and a ground line. The circuit blocks are arrayed with respect to a power supply terminal in order of the noise level at the power input terminals of respective circuit blocks, so that a circuit block having a lower noise level is located near the power supply terminal while a circuit block having a higher noise level is located far from the power supply terminal.

Abstract: A first bypass capacitor interposes between an independent power supply line and an independent ground line provided in each of a plurality of circuit blocks. A second bypass capacitor interposes between a common power supply line and a common ground line.