Patents by Inventor Yasuyuki Kawada

Yasuyuki Kawada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11888035
    Abstract: The silicon carbide semiconductor device includes: a silicon carbide layer; a silicon dioxide layer provided above the silicon carbide layer and containing nitrogen; and a transition region arranged between the silicon carbide layer and the silicon dioxide layer, and containing carbon, oxygen, and nitrogen, wherein the maximum nitrogen concentration in the transition region is 1.0×1020 cm?3 or higher. The maximum nitrogen concentration in the transition region is five or more times higher than the maximum nitrogen concentration in the silicon dioxide layer.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: January 30, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Kawada, Aki Takigawa
  • Patent number: 11600702
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, a gate insulating film, gate electrodes, and an interlayer insulating film. The gate insulating film is formed by performing nitriding and oxidation by at least two sessions of a heat treatment by a mixed gas containing nitric oxide and nitrogen, the gate insulating film being configured by a first gate insulating film that is a silicon nitride layer, a second gate insulating film that is a silicon oxide film, and a third gate insulating film that is a silicon oxide film having a nitrogen area density lower than that of the second gate insulating film.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: March 7, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Kawada
  • Publication number: 20230055755
    Abstract: After trench etching but before formation of a gate insulating film, a 15-minute to 60-minute heat treatment under a mixed gas atmosphere containing nitric oxide gas and nitrogen gas at a temperature from 1200 degrees C. to 1350 degrees C. and a 30-minute to 75-minute heat treatment under a nitrogen gas atmosphere held at the temperature of the 15-minute to 60-minute heat treatment are successively performed, oxidizing etching damage of inner walls of trenches. The total treatment time of the heat treatments includes a total time of at least 90 minutes when the temperature is a predetermined maximum temperature. The oxide layer of the trench inner walls is removed, exposing a clean face. Emission intensity of band edge emission for SiC obtained by CL analysis of surface areas of the inner walls of the trenches is at least equal to the emission intensity of the band edge emission for SiC obtained by the CL analysis of a surface free of dry etching.
    Type: Application
    Filed: June 30, 2022
    Publication date: February 23, 2023
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki KAWADA
  • Publication number: 20220406931
    Abstract: A bottom of a trench is an Si plane or a C plane while sidewalls of the trench are an m-plane. In the trench, a gate electrode is provided via a gate insulating film. The gate insulating film is a HTO film with a thickness of at least 50 nm. By a post-HTO-deposition annealing at a temperature in a range of 1250 degrees C. to 1300 degrees C. under a mixed gas atmosphere containing nitric oxide, nitrogen, and oxygen, the film density of the gate insulating film is within a range of 2.21 g/cm3 to 2.38 g/cm3. The total oxygen flow amount of the mixed gas atmosphere of the post-HTO-deposition annealing is at most 5%. The gate insulating film has a two-layer structure including a low-density film that is within 3 nm from a SiC/SiO2 interface and has a relatively low film density, and a high- density film that is at least 3 nm apart from the SiC/SiO2 interface and has a relatively high film density.
    Type: Application
    Filed: April 22, 2022
    Publication date: December 22, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki KAWADA
  • Patent number: 11515387
    Abstract: A method of manufacturing a silicon carbide substrate having a parallel pn layer. The method includes preparing a starting substrate containing silicon carbide, forming a first partial parallel pn layer on the starting substrate by a trench embedding epitaxial process, stacking a second partial parallel pn layer by a multi-stage epitaxial process on the first partial parallel pn layer, and stacking a third partial parallel pn layer on the second partial parallel pn layer by another trench embedding epitaxial process. Each of the first, second and third partial parallel pn layers is formed to include a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternately disposed in parallel to a main surface of the silicon carbide substrate.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: November 29, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Kawada
  • Patent number: 11430870
    Abstract: After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO2/SiC interface is set to be at most 1.6×1015/cm2 and a nitrogen amount is set to more than 5.0×1014/cm2.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: August 30, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Yasuyuki Kawada, Aki Takigawa
  • Patent number: 11424325
    Abstract: Before formation of gate insulating films, an oblique ion implantation of oxygen into opposing sidewalls of trenches, from a top of an oxide film mask is performed, forming oxygen ion-implanted layers in surface regions of the sidewalls. A peak position of oxygen concentration distribution of the oxygen ion-implanted layers is inside the oxide film mask. After removal of the oxide film mask, HTO films constituting the gate insulating films are formed. During deposition of the HTO films, excess carbon occurring at the start of the deposition of the HTO films and in the gate insulating films reacts with oxygen in the oxygen ion-implanted layers, thereby becoming an oxocarbon and being desorbed. The oxygen ion-implanted layers have a thickness in a direction orthogonal to the sidewalls at most half of the thickness of the gate insulating films, and an oxygen concentration higher than any other portion of the semiconductor substrate.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: August 23, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Kawada
  • Publication number: 20220069089
    Abstract: The silicon carbide semiconductor device includes: a silicon carbide layer; a silicon dioxide layer provided above the silicon carbide layer and containing nitrogen; and a transition region arranged between the silicon carbide layer and the silicon dioxide layer, and containing carbon, oxygen, and nitrogen, wherein the maximum nitrogen concentration in the transition region is 1.0×1020 cm?3 or higher. The maximum nitrogen concentration in the transition region is five or more times higher than the maximum nitrogen concentration in the silicon dioxide layer.
    Type: Application
    Filed: July 27, 2021
    Publication date: March 3, 2022
    Inventors: Yasuyuki KAWADA, Aki TAKIGAWA
  • Publication number: 20220013641
    Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, a gate insulating film, gate electrodes, and an interlayer insulating film. The gate insulating film is formed by performing nitriding and oxidation by at least two sessions of a heat treatment by a mixed gas containing nitric oxide and nitrogen, the gate insulating film being configured by a first gate insulating film that is a silicon nitride layer, a second gate insulating film that is a silicon oxide film, and a third gate insulating film that is a silicon oxide film having a nitrogen area density lower than that of the second gate insulating film.
    Type: Application
    Filed: May 28, 2021
    Publication date: January 13, 2022
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki KAWADA
  • Publication number: 20210234005
    Abstract: Before formation of gate insulating films, an oblique ion implantation of oxygen into opposing sidewalls of trenches, from a top of an oxide film mask is performed, forming oxygen ion-implanted layers in surface regions of the sidewalls. A peak position of oxygen concentration distribution of the oxygen ion-implanted layers is inside the oxide film mask. After removal of the oxide film mask, HTO films constituting the gate insulating films are formed. During deposition of the HTO films, excess carbon occurring at the start of the deposition of the HTO films and in the gate insulating films reacts with oxygen in the oxygen ion-implanted layers, thereby becoming an oxocarbon and being desorbed. The oxygen ion-implanted layers have a thickness in a direction orthogonal to the sidewalls at most half of the thickness of the gate insulating films, and an oxygen concentration higher than any other portion of the semiconductor substrate.
    Type: Application
    Filed: December 30, 2020
    Publication date: July 29, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki KAWADA
  • Publication number: 20210167167
    Abstract: A method of manufacturing a silicon carbide substrate having a parallel pn layer. The method includes preparing a starting substrate containing silicon carbide, forming a first partial parallel pn layer on the starting substrate by a trench embedding epitaxial process, stacking a second partial parallel pn layer by a multi-stage epitaxial process on the first partial parallel pn layer, and stacking a third partial parallel pn layer on the second partial parallel pn layer by another trench embedding epitaxial process. Each of the first, second and third partial parallel pn layers is formed to include a plurality of first-conductivity-type regions and a plurality of second-conductivity-type regions alternately disposed in parallel to a main surface of the silicon carbide substrate.
    Type: Application
    Filed: October 23, 2020
    Publication date: June 3, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki KAWADA
  • Publication number: 20210134961
    Abstract: After trench etching, trench corner portions are rounded by hydrogen annealing at a temperature of at least 1500 degrees C. Next, n-type regions that cause leak current and are formed in inner walls of the trenches by the hydrogen annealing are removed by a heat treatment (hydrogen etching) under a hydrogen atmosphere of a temperature less than 1500 degrees C. and the inner walls are planarized. Next, the inner walls are nitrided by introducing nitrogen into the heat treatment furnace while the temperature of the hydrogen-etching heat treatment decreases, thereby forming a SiN film along the inner walls. Next, an HTO film is formed, as gate insulating films, on the SiN film along the inner walls of the trenches. Thereafter, by PDA, an oxygen amount of an interface section of a SiO2/SiC interface is set to be at most 1.6×1015/cm2 and a nitrogen amount is set to more than 5.0×1014/cm2.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 6, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto UTSUMI, Yasuyuki KAWADA, Aki TAKIGAWA
  • Patent number: 10818771
    Abstract: A plurality of trenches are formed so as to reach a prescribed depth from the surface of an n-type epitaxial layer. A refractory metal carbide film, such as a TaC film is formed via sputtering on the surface of sections (mesa regions) of the n-type epitaxial layer interposed between the adjacent trenches. Sections of the TaC film on the inner walls of the trenches are removed via etching. While the surface of the mesa regions is covered by the TaC film, the inside of the trenches is filled with a p-type epitaxial layer that is grown by CVD, thereby forming a parallel pn structure. Then, sections of the p-type epitaxial layer protruding above the surface of the parallel pn structure and the TaC film above the surface of the mesa regions are ground until top surfaces of n-type regions and p-type regions of the parallel pn structure are exposed.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: October 27, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Kawada
  • Patent number: 10741648
    Abstract: A manufacturing yield and reliability of a semiconductor device including a power semiconductor element is improved. A plurality of trenches DT extending in an x direction and spaced apart from each other in a y direction orthogonal to the x direction are formed in a substrate having a main crystal surface tilted with respect to a <11-20> direction. Also, a super-junction structure is constituted of a p-type column region PC made of a semiconductor layer embedded in the trench DT and an n-type column region NC made of a part of the substrate between the trenches DT adjacent in the y direction, and an angle error between the extending direction of the trench DT (x direction) and the <11-20> direction is within ±?. The ? is determined by {arctan {k× (w/h)}}/13 for the trench having a height of h and a width of w. Herein, the k is at least smaller than 2, preferably 0.9 or less, more preferably 0.5 or less, and still more preferably 0.3 or less.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: August 11, 2020
    Assignees: National Institute of Advanced Industrial Science and Technology, Hitachi, Ltd, Fuji Electric Co., Ltd, Mitsubishi Electric Corporation
    Inventors: Ryoji Kosugi, Shiyang Ji, Kazuhiro Mochizuki, Yasuyuki Kawada, Hidenori Kouketsu
  • Publication number: 20190252517
    Abstract: A plurality of trenches are formed so as to reach a prescribed depth from the surface of an n-type epitaxial layer. A refractory metal carbide film, such as a TaC film is formed via sputtering on the surface of sections (mesa regions) of the n-type epitaxial layer interposed between the adjacent trenches. Sections of the TaC film on the inner walls of the trenches are removed via etching. While the surface of the mesa regions is covered by the TaC film, the inside of the trenches is filled with a p-type epitaxial layer that is grown by CVD, thereby forming a parallel pn structure. Then, sections of the p-type epitaxial layer protruding above the surface of the parallel pn structure and the TaC film above the surface of the mesa regions are ground until top surfaces of n-type regions and p-type regions of the parallel pn structure are exposed.
    Type: Application
    Filed: January 7, 2019
    Publication date: August 15, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Yasuyuki KAWADA
  • Patent number: 10186575
    Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: January 22, 2019
    Assignees: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuyuki Kawada, Shiyang Ji, Ryoji Kosugi, Hidenori Koketsu, Kazuhiro Mochizuki
  • Patent number: 10096470
    Abstract: A method of growing a single-crystal, silicon carbide epitaxial film on a silicon carbide substrate by chemical vapor deposition is disclosed that results in a stress value of the epitaxial film within ±7.8 MPa. For example, from the start of the growth of the epitaxial film until completion, introduction of a source gas including a gas containing silicon, a gas containing carbon, and a gas containing chlorine into a reaction chamber and performing epitaxial growth is alternately performed with suspension of the supply of the gas containing silicon and the gas containing carbon into the reaction chamber while furnace temperature is maintained as is during performing processing in a gas atmosphere containing only hydrogen, or hydrogen and hydrogen chloride, whereby the epitaxial film is grown. Employing such a method enables manufacture of a substrate having a silicon carbide epitaxial film with minimal warpage.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: October 9, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Kawada
  • Publication number: 20180248002
    Abstract: In a silicon carbide semiconductor device, an n-type drift layer is formed on a front surface of an n++-type semiconductor substrate. Next, a trench is formed in the n-type drift layer, from a surface of the n-type drift layer. Next, a p-type pillar region is formed in the trench. A depth of the trench is at least three times a width of the trench. The p-type pillar region is formed by concurrently introducing a p-type first dopant and a gas containing an n-type second dopant incorporated at an atom position different from that of the first dopant.
    Type: Application
    Filed: February 23, 2018
    Publication date: August 30, 2018
    Applicants: FUJI ELECTRIC CO., LTD., MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yasuyuki KAWADA, Shiyang JI, Ryoji KOSUGI, Hidenori KOKETSU, Kazuhiro MOCHIZUKI
  • Patent number: 10032724
    Abstract: On a first epitaxial layer of a first conductivity type or a second conductivity type provided on a front surface of a silicon carbide substrate, a mark indicating a crystal axis direction of the silicon carbide substrate within a margin of error of one degree is provided. The mark is created on the silicon carbide substrate by forming the first epitaxial layer of the first conductivity type or the second conductivity type on the front surface of the silicon carbide substrate, detecting a stacking fault from the first epitaxial layer, and confirming the crystal axis direction of the silicon carbide substrate from the detected stacking fault.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 24, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Kawada, Takeshi Tawara
  • Patent number: 10026610
    Abstract: Provided is a method of manufacturing a silicon carbide semiconductor device with a long carrier lifetime without carrying out an additional step after a SiC single crystal substrate is fabricated using a chemical vapor deposition method. The silicon carbide semiconductor device manufacturing method includes (a) growing a silicon carbide single crystal film at a first temperature on a silicon carbide semiconductor substrate using chemical vapor deposition; (b) cooling the silicon carbide semiconductor substrate from the first temperature to a second temperature, which is lower than the first temperature, in an atmosphere of a carbon-containing gas after growing the silicon carbide crystal film; and (c) subsequently cooling the silicon carbide semiconductor substrate to a third temperature, which is lower than the second temperature, in a hydrogen gas atmosphere.
    Type: Grant
    Filed: April 9, 2015
    Date of Patent: July 17, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Yasuyuki Kawada, Yoshiyuki Yonezawa