Abstract: An information processing system includes an information processing apparatus having a first function, and a server apparatus being configured to communicate with the information processing apparatus via a communication network. The information processing apparatus includes an operation control apparatus being configured to control the first function. The server apparatus transmits operation permission information indicating operation permission for the first function to the information processing apparatus, in response to satisfaction of a predetermined condition related to the information processing apparatus. The operation control apparatus activates the first function, in response to the operation permission information received by the information processing apparatus.

Abstract: An information processing system includes an information processing apparatus having a first function, and a server apparatus being configured to communicate with the information processing apparatus via a communication network. The information processing apparatus includes an operation control apparatus being configured to control the first function. The server apparatus transmits operation permission information indicating operation permission for the first function to the information processing apparatus, in response to satisfaction of a predetermined condition related to the information processing apparatus. The operation control apparatus activates the first function, in response to the operation permission information received by the information processing apparatus.

Abstract: The semiconductor integrated circuit according to the present invention includes a mode switching circuit for switching an operation mode of a main core circuit among a plurality of internal circuits between a normal operation mode and a stand-by mode; and a stand-by canceling circuit for instructing the mode switching circuit to cancel a stand-by mode, and the mode switching circuit and the stand-by canceling circuit are configured to operate in asynchronism with the system clock with stand-by voltage in the stand-by mode. Thus, the semiconductor integrated circuit is capable of achieving operations with reduced power consumption with restrained leakage current by further reducing power source voltage during a stand-by mode, while maintaining advantages of shortening a time required to return from the stand-by mode, and of requiring no additional circuitry, such as non-volatile memory, for returning from the stand-by mode and thus requiring no extra cost.

Abstract: Appropriate shadowing processing is performed even if coordinate conversion calculation values of polygons have errors. A calculation section 5 performs hidden surface removal processing on normal polygons based on visual-point coordinates and depth values from a visual-point coordinate conversion processing unit 1, and updates a pixel memory 6 and a Z-buffer memory 7. Further, based on a comparison result of obtained depth values of each polygon and Z values stored in the Z-buffer memory 7, shadowing is performed only on a coordinate region positioned in front of back-facing shadow polygons and behind front-facing shadow polygons when seen from a visual point, and the pixel memory 6 is updated. As a result, even if coordinate conversion calculation values in graphic data on polygons have errors, an edge portion of the shadow polygons which is not intended to be shadowed is not shadowed.

Abstract: A large-scale integrated circuit according to the present invention includes a plurality of functional blocks for independently performing a signal processing operation, and a selection controlling circuit for generating a first control signal to select one of the plurality of functional blocks, in which the selection controlling circuit includes a control signal generating circuit for generating a second control signal for stopping the operation of its circuit, and the selection controlling circuit generates the first and the second control signals by a command from a different control circuit.

Abstract: The semiconductor integrated circuit according to the present invention includes a mode switching circuit for switching an operation mode of a main core circuit among a plurality of internal circuits between a normal operation mode and a stand-by mode; and a stand-by canceling circuit for instructing the mode switching circuit to cancel a stand-by mode, and the mode switching circuit and the stand-by canceling circuit are configured to operate in asynchronism with the system clock with stand-by voltage in the stand-by mode. Thus, the semiconductor integrated circuit is capable of achieving operations with reduced power consumption with restrained leakage current by further reducing power source voltage during a stand-by mode, while maintaining advantages of shortening a time required to return from the stand-by mode, and of requiring no additional circuitry, such as non-volatile memory, for returning from the stand-by mode and thus requiring no extra cost.

Abstract: A large-scale integrated circuit according to the present invention includes a plurality of functional blocks for independently performing a signal processing operation, and a selection controlling circuit for generating a first control signal to select one of the plurality of functional blocks, in which the selection controlling circuit includes a control signal generating circuit for generating a second control signal for stopping the operation of its circuit, and the selection controlling circuit generates the first and the second control signals by a command from a different control circuit.

Abstract: The image synthesis apparatus 10 includes an anti-aliasing processing circuit 11 for generating a foreground image having a reduced aliasing by blending the color information and blending the alpha information for each dot of the input foreground image, and an image synthesizing circuit 15 for synthesizing the color information of the foreground image having the reduced aliasing and the color information of the background image, using the alpha information of the foreground image having the reduced aliasing.

Abstract: The image synthesis apparatus 10 includes an anti-aliasing processing circuit 11 for generating a foreground image having a reduced aliasing by blending the color information and blending the alpha information for each dot of the input foreground image, and an image synthesizing circuit 15 for synthesizing the color information of the foreground image having the reduced aliasing and the color information of the background image, using the alpha information of the foreground image having the reduced aliasing.

Abstract: A three dimensional image rendering apparatus for rendering polygons forming a three dimensional object on a two dimensional display screen, comprising: a hidden surface removal section for performing a hidden surface removal process by, when a part or all of the pixels forming the two dimensional display screen belong to a first polygon which is closest to a point of view, updating memory contents in an information memory section to information of the first polygon; and a blending section for obtaining, based on edge identification information for indicating whether the respective pixels are located on an edge of the first polygon and a percentage of an area in the respective pixels occupied by the first polygon as part of information of the first polygon, the color information of the respective pixels from color information as another part of the first polygon.

Abstract: Appropriate shadowing processing is performed even if coordinate conversion calculation values of polygons have errors. A calculation section 5 performs hidden surface removal processing on normal polygons based on visual-point coordinates and depth values from a visual-point coordinate conversion processing unit 1, and updates a pixel memory 6 and a Z-buffer memory 7. Further, based on a comparison result of obtained depth values of each polygon and Z values stored in the Z-buffer memory 7, shadowing is performed only on a coordinate region positioned in front of back-facing shadow polygons and behind front-facing shadow polygons when seen from a visual point, and the pixel memory 6 is updated. As a result, even if coordinate conversion calculation values in graphic data on polygons have errors, an edge portion of the shadow polygons which is not intended to be shadowed is not shadowed.