Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.

Abstract: A bias circuit according to the present invention includes: a transistor for supplying a bias current from the emitter of the transistor; an emitter potential generating device for supplying a potential to the emitter of the transistor; a switch element; and a voltage supply circuit for supplying a base voltage to the base of the transistor in response to the on/off of the switch element, wherein the emitter potential generating device generates a potential causing a potential difference between the base and emitter of the transistor to fall below a saturation voltage at the junction of the transistor, even in the case where the base of the transistor is fed with a voltage not lower the saturation voltage at the junction of the transistor.

Abstract: A bias circuit according to the present invention includes: a transistor for supplying a bias current from the emitter of the transistor; an emitter potential generating device for supplying a potential to the emitter of the transistor; a switch element; and a voltage supply circuit for supplying a base voltage to the base of the transistor in response to the on/off of the switch element, wherein the emitter potential generating device generates a potential causing a potential difference between the base and emitter of the transistor to fall below a saturation voltage at the junction of the transistor, even in the case where the base of the transistor is fed with a voltage not lower the saturation voltage at the junction of the transistor.

Abstract: A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

Abstract: The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of

Abstract: The present invention, which aims to provide a gallium arsenide field-effect transistor that can reduce degradation of field-effect transistor characteristics, and to realize miniaturization of the transistor, includes: a substrate; a mesa which includes a channel layer and is formed on the substrate; a source electrode formed on the mesa; a drain electrode; and a gate electrode, wherein, on the mesa, a top pattern is formed in which finger portions of the source electrode and the drain electrode which are formed in comb-shape are located so as to interdigitate, and a gate electrode is formed between the source electrode and the drain electrode, while common portions, which are base parts of the finger portions of the source and drain electrodes, are formed on the surface of the mesa, and the part located below the straight portion which is parallel to the finger portions of the gate electrode is electrically separated from the part located below a corner portion that connects neighboring straight portions of

Abstract: A diode logic circuit which can select a high voltage from among the voltages of a number of control voltage input terminals using a number of diodes made of Schottky junctions is integrally formed on a compound semiconductor substrate on which MESFET stages for switching and for securing isolations have been formed. In addition, the MESFET stages for switching are controlled by the voltages of the number of control voltage input terminals and the MESFET stages for securing isolations are controlled by the OR voltage that is outputted from the diode logic circuit.

Abstract: A method of producing a high nitrogen, ultra low carbon steel suitable to rolling material for use in cold rolled steel sheets having excellent age hardening property by an age hardening treatment after forming by working, with no defects in slabs or steel sheets, reliably, at a reduced cost and with a high productivity is proposed. The method for producing a rolling material for use in ultra low carbon steel sheets at: C≦0.0050 mass % comprises; applying primary decarburization refining to molten iron from a blast furnace, then controlling the composition in the molten steel after primary decarburization refining to a range satisfying the following relation: [mass % N]−0.15[mass % C]≧0.0060,  subsequently conducting secondary decarburization refining to a ultra low carbon concentration region while suppressing denitridation using a vacuum degassing facility, then conducting deoxidation by Al and, further, controlling the composition.

Abstract: A method of producing a high nitrogen, ultra low carbon steel suitable to rolling material for use in cold rolled steel sheets having excellent age hardening property by an age hardening treatment after forming by working, with no defects in slabs or steel sheets, reliably, at a reduced cost and with a high productivity is proposed.