Abstract: A disconnection detecting device includes a confirmation signal outputting module configured to cause a transmission sound signal to be outputted from a signal processing unit, and a detector. The transmission sound signal includes a confirmation signal having a frequency that differs from a frequency band for use in communicating information contained in the transmission sound signal that is sent from the signal processing unit to a communication unit. The detector is configured to detect whether or not a disconnection is occurring in connection wires based on the transmission sound signal including the confirmation signal that is returned from the communication unit to the signal processing unit via the connection wires.

Abstract: A disconnection detecting device includes a confirmation signal outputting module configured to cause a transmission sound signal to be outputted from a signal processing unit, and a detector. The transmission sound signal includes a confirmation signal having a frequency that differs from a frequency band for use in communicating information contained in the transmission sound signal that is sent from the signal processing unit to a communication unit. The detector is configured to detect whether or not a disconnection is occurring in connection wires based on the transmission sound signal including the confirmation signal that is returned from the communication unit to the signal processing unit via the connection wires.

Abstract: Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied by the multiplier, a control circuit detects the number of consecutive zeros from the lowest-order bit of the data and performs control, on the basis of the detected number of the consecutive zeros and for each flip-flop circuit, as to whether or not the clock pulse should be supplied to the flip-flop circuit. The control circuit obtains an integral quotient value x by dividing by the number n the sum between the detected numbers for the first and second numeric value data, to stop the clock pulse supply to a particular number x of flip-flop circuit counted from the lowest-order.

Abstract: A sampling frequency converter has a buffer that stores data in response to a write request signal, and outputs stored data in order from the oldest data in response to a read request signal. An interpolation unit sequentially receives data from an external source, performs an interpolation operation at a generation timing of a write request signal for calculating interpolated data from a specified number of the most recently received data, and supplies the interpolated data to the buffer. A writing speed adjusting unit recurrently generates a write request signal at a time rate determined according to frequency control information. A speed correction pointer increases a pointer value each time a write request signal is generated, and decreases the pointer value each time a read request signal is generated. A frequency control unit corrects the frequency control information based on the pointer value of the speed correction pointer.

Abstract: An audio signal processor is composed of a data path unit, a mode register and a state machine unit. The data path unit applies one or more arithmetical operation to an audio signal for performing signal processing of the audio signal. The mode register stores mode information specifying the signal processing to be performed by the data path unit. The state machine unit sequentially feeds control signals according to the mode information for enabling the data path unit to apply one or more arithmetical operation to the audio signal so as to perform the signal processing. The performed signal processing is composed of the one or more arithmetical operations, and is specified by the mode information stored in the mode register.

Abstract: A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.

Abstract: Register includes flip-flop circuits each constructed to retain data of n bit in synchronism with a clock pulse, the register retaining a multiplication result of a multiplier dividedly by the flip-flop circuits, n bit per flip-flop circuit. For each of a first and second numeric value data to be multiplied by the multiplier, a control circuit detects the number of consecutive zeros from the lowest-order bit of the data and performs control, on the basis of the detected number of the consecutive zeros and for each flip-flop circuit, as to whether or not the clock pulse should be supplied to the flip-flop circuit. The control circuit obtains an integral quotient value x by dividing by the number n the sum between the detected numbers for the first and second numeric value data, to stop the clock pulse supply to a particular number x of flip-flop circuit counted from the lowest-order.

Abstract: Periodically sampled digital data (e.g., digital audio data) are once stored in a work RAM and are then subjected to signal processing such as arithmetic operations using coefficients. A primary accumulator register stores results of arithmetic operations. A secondary accumulator register is specialized in handling a relatively high processing load (e.g., down-sampling) having a plurality of steps, which are distributed and appropriately assigned to a plurality of periods in response to output timings. In order to execute other processing in each period, intermediate results of arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register. The number of steps assigned to each period is appropriately changed in response to interruption of the other processing, whereas the relatively high processing load is given a first priority in comparison with the other processing.

Abstract: A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.

Abstract: Periodically sampled digital data (e.g., digital audio data) are once stored in a work RAM and are then subjected to signal processing such as arithmetic operations using coefficients. A primary accumulator register stores results of arithmetic operations. A secondary accumulator register is specialized in handling a relatively high processing load (e.g., down-sampling) having a plurality of steps, which are distributed and appropriately assigned to a plurality of periods in response to output timings. In order to execute other processing in each period, intermediate results of arithmetic operations regarding the relatively high processing load are temporarily stored in the secondary accumulator register. The number of steps assigned to each period is appropriately changed in response to interruption of the other processing, whereas the relatively high processing load is given a first priority in comparison with the other processing.

Abstract: There are provided a musical tone-generating apparatus which neither requires hardware having an increased circuit size nor imposes a heavy burden on a CPU thereof, and a mobile terminal apparatus including the musical tone-generating apparatus, as well as a musical tone-generating method, and a storage medium storing a program for executing the method. A CPU converts music contents data stored in a RAM to hardware tone generator control data, stores the resulting data into the RAM. In reproduction, the CPU reads out and sends the hardware tone generator control data to a hardware tone generator. A data decoder circuit of the hardware tone generator sequentially reads out the hardware tone generator control data from a FIFO and separates the read data into time management information and data of a parameter for generation of a musical tone, and sets the time management information to a counter.

Abstract: There is provided a musical tone reproducing apparatus, which stores tone color parameters in a general-purpose storage means, to thereby shorten the time taken for a tone color changing process. A CPU 10 registers a tone color parameter group that has been read out from a RAM 11 in a tone generator memory 30, which is a general-purpose memory, in advance. The tone color parameters required when a tone generation core 33 carries out musical tone reproduction are stored in a cache memory 32 for all channels. Upon the CPU 10 giving a tone color changing command to a controller 31, a specified tone color parameter is read out from the tone generator memory 30. The tone color parameter for a specified channel in the cache memory 32 is then rewritten with the read out tone color parameter. The tone generation core 33 reads out from the cache memory 32 the rewritten tone color parameter set for each channel, and hence musical tone reproduction with a changed tone color is carried out.

Abstract: There is provided a musical tone reproducing apparatus which is capable of recovering proper timing of musical tone generation even in a situation where processing of events takes much time such that the sounding timing of musical tones is delayed. Duration data read out from a FIFO 30 are added together by a duration forward counter 32b. A comparator circuit 32d compares the count value of an absolute time counter 32c and the count value of the duration forward counter 32b, and delivers the comparison result i to a FIFO controller 3 when the former becomes equal to or more than the latter. The FIFO controller 31 causes the FIFO 30 to read out event information and delivers the same to a decoder 32a, which in turn converts the event information into tone generator control data having a format peculiar to a tone generator 33 and delivers the same data to a register write controller 32e.

Abstract: A portable telephone downloads from the music download center the music data that contain tone color data, tempo data, and a series of note data and rest data with respect to at least a single musical tune. A CPU outputs to an interface the tone color data, and the series of note data and rest data at a tempo designated by the tempo data. The interface converts these data in the prescribed format (e.g., MIDI format), so that the converted data are output to the external playback device (e.g., synthesizer) via a cable or by radio communication.

Abstract: A digital signal processor is adapted to a working RAM, which is capable of storing a plurality of data in a rewritable manner and whose storage area is divided into a plurality of sub-areas that are designated by addresses in read/write operations, wherein an operation circuit performs calculations on the data of the working RAM in accordance with a program, and wherein upon detection of a non-access event in which the program does not need to access the working RAM, a write circuit compulsorily writes ‘0’ into the working RAM with regard to each of the prescribed addresses of the prescribed sub-areas subjected to initialization, which are designated by address data. Thus, it is possible to actualize the selective initialization on the prescribed sub-areas within the working RAM without increasing the scale of the peripheral circuitry, without requiring complicated controls, and without increasing the overall processing time therefor.

Abstract: An audio signal processor is composed of a data path unit, a mode register and a state machine unit. The data path unit applies one or more arithmetical operation to an audio signal for performing signal processing of the audio signal. The mode register stores mode information specifying the signal processing to be performed by the data path unit. The state machine unit sequentially feeds control signals according to the mode information for enabling the data path unit to apply one or more arithmetical operation to the audio signal so as to perform the signal processing. The performed signal processing is composed of the one or more arithmetical operations, and is specified by the mode information stored in the mode register.

Abstract: There is provided a musical tone reproducing apparatus which is capable of recovering proper timing of musical tone generation even in a situation where processing of events takes much time such that the sounding timing of musical tones is delayed. Duration data read out from a FIFO 30 are added together by a duration forward counter 32b. A comparator circuit 32d compares the count value of an absolute time counter 32c and the count value of the duration forward counter 32b, and delivers the comparison result i to a FIFO controller 3 when the former becomes equal to or more than the latter. The FIFO controller 31 causes the FIFO 30 to read out event information and delivers the same to a decoder 32a, which in turn converts the event information into tone generator control data having a format peculiar to a tone generator 33 and delivers the same data to a register write controller 32e.

Abstract: The present invention is directed to a power control circuit for reducing wasteful power consumption of an electronic apparatus such as a digital signal processor. More specifically, a preferred embodiment of the present invention includes a processing detecting device that detects occurrence of an index indicative of a start of execution of a process by the electronic apparatus, a processing termination detecting device for detecting a termination of the processes, and a power control device that responds to the detection of the termination of the process for reducing the power consumption by at least one circuit element of the electronic apparatus for a time period after the termination of the processing, and until the next occurrence of the index indicative of another start of execution of a process.

Abstract: A portable telephone downloads from the music download center the music data that contain tone color data, tempo data, and a series of note data and rest data with respect to at least a single musical tune. A CPU outputs to an interface the tone color data, and the series of note data and rest data at a tempo designated by the tempo data. The interface converts these data in the prescribed format (e.g., MIDI format), so that the converted data are output to the external playback device (e.g., synthesizer) via a cable or by radio communication.

Abstract: A digital signal processor and digital signal processing method are provided, which are capable of performing plural kinds of signal processing, and also performing processing for storing sampled data in a manner corresponding to respective kinds of signal processing with a small amount of hardware even in the case where the manner of storing and reading sampled data to be processed with respect to a memory device is different between the plural kinds of signal processing. A storage device stores plural kinds of sampled data corresponding, respectively, to plural kinds of signal processing. A counter updates a count value thereof every sampling period and generates the updated count value as a basic address.