Patents by Inventor Yasuyuki Nagasoe
Yasuyuki Nagasoe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10372372Abstract: A storage system includes first storage devices to provide storage areas of a first tier and for which a life usage rate is determined based on an erase count and a guaranteed maximum erase count, second storage devices to provide storage areas of a second tier and for which a guaranteed maximum erase count is not specified, and a controller to perform data reallocation between the first tier and the second tier. The controller determines a weight for a read access and a weight for a write access from a host based on life usage rates of the first storage devices, and determines whether to relocate data stored in the second tier to the first tier based on the weight for a read access, the weight for a write access, a read count for the data in a period, and a write count for the data in the period.Type: GrantFiled: April 22, 2015Date of Patent: August 6, 2019Assignee: Hitachi, Ltd.Inventors: Tatsuya Nakamura, Shintarou Inoue, Yasuyuki Nagasoe
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Publication number: 20180067687Abstract: A storage system includes first storage devices to provide storage areas of a first tier and for which a life usage rate is determined based on an erase count and a guaranteed maximum erase count, second storage devices to provide storage areas of a second tier and for which a guaranteed maximum erase count is not specified, and a controller to perform data reallocation between the first tier and the second tier. The controller determines a weight for a read access and a weight for a write access from a host based on life usage rates of the first storage devices, and determines whether to relocate data stored in the second tier to the first tier based on the weight for a read access, the weight for a write access, a read count for the data in a period, and a write count for the data in the period.Type: ApplicationFiled: April 22, 2015Publication date: March 8, 2018Inventors: Tatsuya NAKAMURA, Shintarou INOUE, Yasuyuki NAGASOE
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Patent number: 8751766Abstract: A storage system including: a plurality of storage devices; a volatile memory which temporarily stores data; a nonvolatile memory; a battery saving power; a cache control unit which sets, according to battery charging rate of the battery, a part of the data stored in the volatile memory as save target data which are to be saved to the nonvolatile memory when power interruption occurs, and saves the part of the data, which is set as the save target data, to the nonvolatile memory by using power of the battery when power interruption occurs.Type: GrantFiled: September 12, 2012Date of Patent: June 10, 2014Assignee: Hitachi, Ltd.Inventors: Naoki Inoue, Yasuyuki Nagasoe
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Patent number: 8489918Abstract: When a failure has occurred, the situation is dealt with promptly according to this invention. As triggered by detection of a failure in any specified processor package of a plurality of processor packages, a processor for the specified processor package is temporarily substituted with a processor for another processor package, as an assignment destination of ownership which is assigned to the processor for the specified processor package, instead of actually transferring the ownership, thereby making the transition to an ownership-substituted state; and as triggered by an event that the failure is no longer detected in the specified processor package, a processor for the other processor package cancels the ownership-substituted state.Type: GrantFiled: April 21, 2010Date of Patent: July 16, 2013Assignee: Hitachi, Ltd.Inventors: Koji Watanabe, Ryu Takada, Kei Satoh, Yasuyuki Nagasoe
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Patent number: 8423796Abstract: A storage device and a data processing method of the storage device are provided which can prevent leaking of data attributed to stealing or taking out of a disk device. The storage device includes: disk adapters, each connected to HDDs which constitute one or more RAID groups; and a management part which manages a storage area provided by the HDDs in a state that the storage area is divided into logical storage areas, and manages the RAID groups. The management part sets an encryption state indicative of whether or not the data is to be encrypted with respect to the RAID groups when all of the disk adapters are connected to the HDDs which belong to the RAID groups are encryption adapters. The management part also encrypts, based on the encryption state set with respect to the RAID groups, and stores the encrypted data in the HDD.Type: GrantFiled: September 22, 2008Date of Patent: April 16, 2013Assignee: Hitachi, Ltd.Inventors: Shin Nishihara, Shuichi Yagi, Yasuyuki Nagasoe
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Patent number: 8380925Abstract: The present invention allows load balancing between processor units without impacting the I/O performance of the storage system. An LDEV owner right is changed on the basis of static information that does not dynamically change in accordance with the number of I/O commands relating to a LDEV. This information is a load index determined for each LDEV. Any of a plurality of processor units selects a processor unit that is to be an assignment destination of the owner right of a target LDEV, based on the load index that has been assigned to each processor unit and the load index of the target LDEV, and assigns this owner right to the selected processor unit. The load index assigned to the processor unit is a value based on the load index of one or more LDEV respectively corresponding to one or more owner rights assigned to this processor unit.Type: GrantFiled: May 22, 2009Date of Patent: February 19, 2013Assignee: Hitachi, Ltd.Inventors: Norio Shimozono, Yasuyuki Nagasoe
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Publication number: 20130007342Abstract: A storage system including: a plurality of storage devices; a volatile memory which temporarily stores data; a nonvolatile memory; a battery saving power; a cache control unit which sets, according to battery charging rate of the battery, a part of the data stored in the volatile memory as save target data which are to be saved to the nonvolatile memory when power interruption occurs, and saves the part of the data, which is set as the save target data, to the nonvolatile memory by using power of the battery when power interruption occurs.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Inventors: Naoki INOUE, Yasuyuki NAGASOE
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Patent number: 8275930Abstract: The present invention allows a save target stored in a volatile memory, to be reliably saved to a non-volatile memory and reduces the time required for the save processing as much as possible. The charging state of a battery is regularly of irregularly checked. It is determined, according to the checked charging state, which information element stored in the volatile memory should be made a save target at the time of the occurrence of a power interruption. Among a plurality of information elements stored in the volatile memory, a predetermined information element is made a non-save target of save processing, according to a state related to the predetermined information element.Type: GrantFiled: December 4, 2008Date of Patent: September 25, 2012Assignee: Hitachi, Ltd.Inventors: Naoki Inoue, Yasuyuki Nagasoe
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Publication number: 20120117321Abstract: When a failure has occurred, the situation is dealt with promptly according to this invention. As triggered by detection of a failure in any specified processor package of a plurality of processor packages, a processor for the specified processor package is temporarily substituted with a processor for another processor package, as an assignment destination of ownership which is assigned to the processor for the specified processor package, instead of actually transferring the ownership, thereby making the transition to an ownership-substituted state; and as triggered by an event that the failure is no longer detected in the specified processor package, a processor for the other processor package cancels the ownership-substituted state.Type: ApplicationFiled: April 21, 2010Publication date: May 10, 2012Applicant: HITACHI, LTD.Inventors: Koji Watanabe, Ryu Takada, Kei Satoh, Yasuyuki Nagasoe
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Publication number: 20110225345Abstract: The present invention allows a save target stored in a volatile memory, to be reliably saved to a non-volatile memory and reduces the time required for the save processing as much as possible. The charging state of a battery is regularly of irregularly checked. It is determined, according to the checked charging state, which information element stored in the volatile memory should be made a save target at the time of the occurrence of a power interruption. Among a plurality of information elements stored in the volatile memory, a predetermined information element is made a non-save target of save processing, according to a state related to the predetermined information element.Type: ApplicationFiled: December 4, 2008Publication date: September 15, 2011Applicant: HITACHI, LTD.Inventors: Naoki Inoue, Yasuyuki Nagasoe
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Patent number: 7991974Abstract: Access to a plurality of logical devices is enabled regardless of the number of ports provided in a storage system and the number of logical devices that can be allocated to a single port, thereby improving the usability of the logical devices. A storage system comprises a plurality of logical devices, a target device which is the object of access from a computer, and a juke box system for allocating one of the plurality of logical devices to the target device. The juke box system changes the logical device that is allocated to the target device in accordance with a request from the computer.Type: GrantFiled: June 9, 2010Date of Patent: August 2, 2011Assignee: Hitachi, Ltd.Inventors: Yoshiaki Eguchi, Yasutomo Yamamoto, Yasuyuki Nagasoe
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Patent number: 7987329Abstract: A storage system is utilized to its fullest storage capacity by setting a write inhibitive attribute to a desired storage area of the storage system. The storage system has a logical volume in which data is stored and a control device which controls access to the data stored in the logical volume. A first area of a desired size is set in the logical volume, and an access control attribute is set to the first area. In response to a request made by a computer to perform access to the logical volume, the control device notifies the computer that the control device does not perform the access when an area designated by the access request contains at least a part of the first area and the access control attribute set to the first area inhibits the type of the access requested.Type: GrantFiled: December 2, 2008Date of Patent: July 26, 2011Assignee: Hitachi, Ltd.Inventors: Shunji Kawamura, Hisao Homma, Yasuyuki Nagasoe
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Publication number: 20100306465Abstract: The present invention allows load balancing between processor units without impacting the I/O performance of the storage system. An LDEV owner right is changed on the basis of static information that does not dynamically change in accordance with the number of I/O commands relating to a LDEV. This information is a load index determined for each LDEV. Any of a plurality of processor units selects a processor unit that is to be an assignment destination of the owner right of a target LDEV, based on the load index that has been assigned to each processor unit and the load index of the target LDEV, and assigns this owner right to the selected processor unit. The load index assigned to the processor unit is a value based on the load index of one or more LDEV respectively corresponding to one or more owner rights assigned to this processor unit.Type: ApplicationFiled: May 22, 2009Publication date: December 2, 2010Applicant: HITACHI, LTD.Inventors: Norio Shimozono, Yasuyuki Nagasoe
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Publication number: 20100250886Abstract: Access to a plurality of logical devices is enabled regardless of the number of ports provided in a storage system and the number of logical devices that can be allocated to a single port, thereby improving the usability of the logical devices. A storage system comprises a plurality of logical devices, a target device which is the object of access from a computer, and a juke box system for allocating one of the plurality of logical devices to the target device. The juke box system changes the logical device that is allocated to the target device in accordance with a request from the computer.Type: ApplicationFiled: June 9, 2010Publication date: September 30, 2010Applicant: HITACHI, LTD.Inventors: Yoshiaki Eguchi, Yasutomo Yamamoto, Yasuyuki Nagasoe
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Patent number: 7757058Abstract: Access to a plurality of logical devices is enabled regardless of the number of ports provided in a storage system and the number of logical devices that can be allocated to a single port, thereby improving the usability of the logical devices. A storage system comprises a plurality of logical devices, a target device which is the object of access from a computer, and a juke box system for allocating one of the plurality of logical devices to the target device. The juke box system changes the logical device that is allocated to the target device in accordance with a request from the computer.Type: GrantFiled: April 30, 2008Date of Patent: July 13, 2010Assignee: Hitachi, Ltd.Inventors: Yoshiaki Eguchi, Yasutomo Yamamoto, Yasuyuki Nagasoe
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Patent number: 7739454Abstract: The present invention partitions a cache region of a storage subsystem for each user and prevents interference between user-dedicated regions. A plurality of CLPR can be established within the storage subsystem. A CLPR is a user-dedicated region that can be used by partitioning the cache region of a cache memory. Management information required to manage the data stored in the cache memory is allocated to each CLPR in accordance with the attribute of the segment or slot. The clean queue and clean counter, which manage the segments in a clean state, are provided in each CLPR. The dirty queue and dirty counter are used jointly by all the CLPR. The free queue, classification queue, and BIND queue are applied jointly to all the CLPR, only the counters being provided in each CLPR.Type: GrantFiled: June 12, 2007Date of Patent: June 15, 2010Assignee: Hitachi, Ltd.Inventors: Sachiko Hoshino, Takashi Sakaguchi, Yasuyuki Nagasoe, Shoji Sugino
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Publication number: 20100031062Abstract: The present invention provides a storage device and a data processing method of the storage device which can prevent leaking of data attributed to stealing or taking out of a disk device. A storage device includes: a plurality of disk adapters each of which is connected to HDDs which constitutes at least one RAID group; and a management part which manages a storage area provided by the plurality of HDD in a state that the storage area is divided into a plurality of logical storage areas, and manages the plurality of RAID groups. The management part sets an encryption state indicative of whether or not the data is to be encrypted with respect to the RAID group when all of the disk adapters connected to the HDD which belong to the RAID group are the encryption adapters the data, and the encryption adapter encrypts, based on the encryption state set with respect to the RAID group, and stores the encrypted data in the HDD.Type: ApplicationFiled: September 22, 2008Publication date: February 4, 2010Inventors: Shin Nishihara, Shuichi Yagi, Yasuyuki Nagasoe
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Publication number: 20090327758Abstract: A storage apparatus is provided, which allows a user to properly use an encrypted text and a plain text even when the storage apparatus has an encrypting function. An adaptor controlling transmission and reception of data to and from a memory device is provided with an encrypting function. Data requiring no encryption is transmitted to an adaptor having no encrypting function, and data to be encrypted is transmitted to the adaptor having an encrypting function. Thus, a user of the storage apparatus can properly use an encrypted text and a plain text.Type: ApplicationFiled: August 15, 2008Publication date: December 31, 2009Inventors: Toshimitu SAKANAKA, Shuichi YAGI, Yasuyuki NAGASOE, Kenichi NISHIKAWA
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Patent number: 7594071Abstract: The present invention carries out cache management in such a manner that the management region required for cache management does not increase, and neither does the performance decline. It is possible to combine use of both a hierarchical directory method and a hash directory method, in order to manage cache data. In a hierarchical directory method, the desired data is retrieved by referring to respective tables T1 to T7, in succession. In a hash directory method, the desired data is reached by referring to a hash table TI0 and tables T4 to T7. Access conflicts between the respective methods are avoided by using the EDEV number and a portion of the VDEV number for a hash key. By combining use of both of these methods, it is possible to respond to cases where the storage capacity of the storage system has been increased, without having to raise the management region, and without causing a decline in performance.Type: GrantFiled: July 28, 2006Date of Patent: September 22, 2009Assignee: Hitachi, Ltd.Inventors: Takashi Sakaguchi, Sachiko Hoshino, Yasuyuki Nagasoe
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Publication number: 20090089528Abstract: A storage system is utilized to its fullest storage capacity by setting a write inhibitive attribute to a desired storage area of the storage system. The storage system has a logical volume in which data is stored and a control device which controls access to the data stored in the logical volume. A first area of a desired size is set in the logical volume, and an access control attribute is set to the first area. In response to a request made by a computer to perform access to the logical volume, the control device notifies the computer that the control device does not perform the access when an area designated by the access request contains at least a part of the first area and the access control attribute set to the first area inhibits the type of the access requested.Type: ApplicationFiled: December 2, 2008Publication date: April 2, 2009Inventors: Shunji Kawamura, Hisao Hommma, Yasuyuki Nagasoe