Patents by Inventor Yasuyuki NINOMIYA

Yasuyuki NINOMIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MEMORY CONTROL AND DATA PROCESSING USING MEMORY ADDRESS GENERATION BASED ON DIFFERENTIAL ADDRESSES
    Publication number: 20160070642
    Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 10, 2016
    Inventor: Yasuyuki NINOMIYA
  • Memory control device, memory control method, data processing device, and image processing system
    Patent number: 9183131
    Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: November 10, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yasuyuki Ninomiya
  • MEMORY CONTROL DEVICE, MEMORY CONTROL METHOD, DATA PROCESSING DEVICE, AND IMAGE PROCESSING SYSTEM
    Publication number: 20150058581
    Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
    Type: Application
    Filed: November 3, 2014
    Publication date: February 26, 2015
    Inventor: Yasuyuki NINOMIYA
  • Memory control and data processing using memory address generation based on differential addresses
    Patent number: 8880848
    Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Yasuyuki Ninomiya
  • MEMORY CONTROL DEVICE, MEMORY CONTROL METHOD, DATA PROCESSING DEVICE, AND IMAGE PROCESSING SYSTEM
    Publication number: 20130097393
    Abstract: A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
    Type: Application
    Filed: September 14, 2012
    Publication date: April 18, 2013
    Inventor: Yasuyuki NINOMIYA